ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

1
ECE 3110 Introduction to Digital
SystemsChapter 6 Combinational Logic Design
Practices
XOR, Parity Circuits, Comparators
2
Exclusive OR and Exclusive NOR Gates

• XOR
• XNOR
• Truth Table
  
  XOR X Y XOR XNOR 0
  0 0 1 0 1 1
  0 1 0 1 0
  1 1 0 1
  
  XOR

X
F
Y
X
F
Y
3
XOR and XNOR Symbols

• Equivalent Symbols of XOR gate
• Equivalent Symbols of XNOR gate

Any 2 signals (inputs or outputs) may be
complemented without changing the resulting
logic function
4
SSI XOR and XNOR

• 74x86 4 XOR gates
• 74x266 4 XNOR gates with open collector or
  open drain output

5
XOR Application Parity Circuit

• Odd Parity Circuit The output is 1 if odd
  number of inputs are 1
• Even Parity Circuit The output is 1 if even
  number of inputs are 1
• Example 4-bit Parity Circuit
• Daisy-Chain Structure
  Tree structure Input 1101
  Odd Parity output 1
  Even Parity output 0

EVEN
ODD
6
MSI Parity Circuit 74x280
7
Parity-Checking Application memory
8
Comparators

• Compares Two binary words and indicate if they
  are equalMagnitude Comparators

Comparator
A
AB?
B
AB
A
Comparator
AgtB
B
AltB
9
Equality Comparators

• 1-bit comparator

10
Iterative Comparator
11
Multi-bit Iterative Comparator
12
MSI Comparator 74x85

• 4 bit comparator
• 3 outputs AB, AltB, AgtB
• 3 Cascading inputs
• Functional Output equations (AgtB OUT)
  (AgtB)(AB).(AgtB IN) (AltB OUT) (AltB)(AB).(AltB
  IN) (AB OUT) (AB).(AB IN)
• Cascading inputs initial values (AB IN)
  1(AgtB IN) 0(AltB IN) 0

74x85
AltBIN
AltBOUT
ABIN
AB OUT
AgtBIN
AgtBOUT
A0
B0
A1
B1
A2
B2
A3
B3
13
8 bit Comparator
5V
74x85
74x85
AltBIN
AltBOUT
AltBIN
AltBOUT
AltB
ABIN
AB OUT
ABIN
AB OUT
AB
AgtBIN
AgtBOUT
AgtBIN
AgtBOUT
AgtB
A0
A0
A0
A4
B0
B0
B0
B4
A1
A1
A1
A5
B1
B1
B1
B5
A2
A2
A2
A6
B2
B2
B2
B6
A3
A3
A3
A7
B3
B3
B3
B7
Most Significant bits
Least Significant bits
14
8-bit Magnitude Comparator
15
Other conditions
16
Next

• Adders, subtractors, ALUs
• Reading Wakerly CH-6.10-6.11