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Microinstructions

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No memory ops, so read=write=fetch=0. No shifting, so SLL8=SRA1=0. No branching, so JAMZ=JAMN=0 ... j. BIPUSH 1. ISUB. ISTORE j. GO TO L2. L1: BIPUSH 0. ISTORE ... – PowerPoint PPT presentation

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Title: Microinstructions


1
Microinstructions
  • Microinstruction not same as instruction
  • Contains all the control signals
  • So far, we need 29 of them
  • 9 for C bus enabling
  • 9 for B bus enabling
  • 8 for ALU, shifter control
  • 3 for read/write/fetch control

2
IJVM Microinstruction
3
Microinstruction Practice
  • SP SP 1
  • TOS PC CPP LV OPC
  • TOS CPP / 2 (hint use SRA1 bit)

4
SP SP 1
  • Load SP onto B bus, so B0100
  • ALU does B 1 op, so ALU110101
  • Store C bus into SP, so C000001000
  • No memory ops, so readwritefetch0
  • No shifting, so SLL8SRA10
  • No branching, so JAMZJAMN0
  • JMPC, Next_Address indicate whats next

5
TOS PC CPP LV OPC
  • This requires three microinstruction cycles
  • Cycle 1 HCPP
  • Load CPP onto B bus B0110
  • ALU passes B thru ALU010100
  • Store C bus into H C100000000
  • Cycle 2 HHLV
  • Load LV onto B bus B0101
  • ALU does AB ALU111100
  • Store C bus into H C100000000
  • Cycle 3 TOSPCHOPC
  • Load OPC onto B bus B1000
  • ALU does AB ALU111100
  • Store C bus into TOS and PC C001000100

6
TOS CPP / 2
  • Load CPP onto B bus B0110
  • ALU passes B thru ALU010100
  • Shifter does shift-right arithmetic SRA11
  • Store C bus into TOS, so C001000000

7
Memory Operations
  • For data read/write MAR, MDR
  • One for actual data and one for address
  • Both are 32-bit (MDR has 4 bytes of data)
  • MAR has address of first of 4 bytes
  • For fetching instructions PC, MBR
  • PC is for 32-bit addresses
  • MBR is for an 8-bit instruction
  • MBR receives the byte addressed by PC
  • B bus prepends 0s or sign to MBR for 32 bits

8
MAR Mapping
9
Reads and Writes
  • Read
  • MAR to RAM address
  • RAM data (32 bits, word boundary) to MDR
  • PC, MBR disabled
  • Write
  • MAR to RAM address
  • MDR to RAM data (32 bits, word boundary)
  • PC, MBR disabled

10
Fetches
  • PC to RAM address
  • RAM data (8 bits, byte boundary) to MBR
  • MAR, MDR disabled

11
Beware of Read Delay
  • A common program assignment Z X Y
  • This translates to
  • Read X into R1 (RAM read)
  • Read Y into R2 (RAM read)
  • Add R1 and R2
  • Store sum in Z (RAM write)
  • Problem comes in at Add statement
  • R1, R2 may not be ready!

12
Building in Delays
  • Solution is to plan a delay
  • For IJVM, need to delay one clock cycle
  • Most CPUs need much longer delays
  • Read initiated at end of clock cycle 1
  • Do something else at clock cycle 2
  • Use result of read at clock cycle 3 (or later)

13
Building in a Read Delay
  • So the statement Z X Y becomes
  • Read X into R1 (RAM read)
  • Read Y into R2 (RAM read)
  • Do something else (hopefully useful)
  • Add R1 and R2
  • Store sum in Z (RAM write)
  • Note Z is not changed until a cycle later
  • Also note delay for X was already in place

14
Ordering Microinstructions
  • if (CPP LV) TOS 1
  • else OPC LV
  • PC PC 1
  • H LV (ADDR76)
  • CPP - H (ADDR80 and JAMZ 1)
  • PC PC 1
  • 80 OPC LV (ADDR77)
  • 180 TOS 1 (ADDR77)

15
Choosing Next Microinstruction
  • Branching typically uses condition codes
  • N, Z bits set for negative, zero results
  • JAMN, JAMZ bits initiate tests for N, Z
  • Together, a branch is established
  • Use ADDR alone unless
  • (JAMN and N) or (JAMZ and Z) 1
  • ADDR modified if a JAM test succeeds
  • MPC can also be loaded from MBR

16
From Micro- to Macro-
  • Each machine instruction is itself a program
  • Control store has microinstructions
  • 1 instruction sequence of microinstructions
  • Some Intel machine instructions (string related)
    have hundreds of micro-ops!
  • Most, however, are 4 or less
  • The longer sequences are transferred to microcode
    ROM

17
Some IJVM Machine Instructions
  • Each machine instruction has a op code (address)
  • POP (0x57) - delete word
  • IADD (0x60) - add two words
  • IINC (0x84) - add a constant to a word
  • IAND (0x7E) - and two words
  • IF_ICMPEQ (0x9F) - branch if equal
  • SWAP (0x5F) - exchange values
  • Address indicates starting point in control store

18
The IADD Instruction
iadd1 MAR SP SP - 1 rd iadd2 H
TOS iadd3 MDR TOS MDR H wr goto Main1
Practice show how the registers and
memorychanges before and after each
microinstruction.
19
The POP Instruction
pop1 MAR SP SP - 1 rd pop2 pop3 TOS
MDR goto Main1
Practice show how the registers and
memorychanges before and after each
microinstruction.
20
Translating High-Level to Assembler
ILOAD j ILOAD k IADD ISTORE i ILOAD
i BIPUSH 3 IF_ICMPEQ L1 ILOAD j BIPUSH
1 ISUB ISTORE j GO TO L2 L1 BIPUSH 0 ISTORE
k L2
i j k if (i 3) k 0 else j j - 1
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