HardwareAssisted Simulation and Evaluation of IP Cores Using FPGAbased Rapid Prototyping Boards

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Hardware-Assisted Simulation and Evaluation of IP
CoresUsing FPGA-based Rapid Prototyping Boards

• R. Siripokarpirom and F. Mayer-Lindenberg
• Department of Distributed Systems
• Technical University Hamburg-Harburg (TUHH)
• Hamburg, Germany
• RSP04, Geneva, Switzerland, 28-30 June 2004

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Outline

• Motivation and Focus of this Work
• A HW-SW Infrastructure for Co-Simulation/Emulatio
  n of IP Cores
• A Case Study and Discussion of Results
• Conclusions and Perspectives

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Motivations

• The concept of HW emulation is not new.
• Several commercial HW emulators do exist.
• either custom processor or FPGA based technology
• high logic capacity (gt10M logic gates)
• connected to software test benches or simulators
• very expensive
• long setup time (e.g. compile time)

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Motivations
FPGA Boards
Can I use any FPGA prototyping board (that I
already have) together with a logic simulator for
functional verification and evaluation of IP
cores in real hardware?

• a wide price spectrum
• custom-built or commercial
• different forms board components
• mainly used for prototyping
• can be used for HW emulation / simulation
  acceleration (require board-specific
  supporting SW provided by the vendors)

I need a unified HW SW environment that can
support different FPGA boards.
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Focus of This Work

• To offer a low-cost, easy-to-use solution for
  functional verification evaluation of IP cores
• target FPGA designs (but not ASIC/SOC designs)
• To provide a unified HW/SW environment for
  different FPGA boards
• To find an acceptable trade-off among various
  aspects
• e.g., simulation speed, design complexity, logic
  capacity and costs

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HW SW Infrastructure for Co-Simulation/Emulatio
n

• Hardware Infrastructure
• FPGA-to-PC interfacing
• access control of IP blocks mapped to the FPGA
• Software Environment
• logic simulation and testbenches
• interaction with the hardware IP blocks
• visualization and analysis of simulation results

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FPGA-to-PC Interfacing

• Possible choices
• RS232, Parallel Port, USB, PCI, Ethernet, ...
• Implement the interface by using the JTAG
  standard and a parallel download cable.
• Xilinx Parallel Cable III
• Altera ByteBlasterMV
• Pro Con of this approach
• use what you (usually) have, no extra efforts
  required.
• low data transfer rate (due to bit-serial data
  transfer)

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Accessing and Controlling IP Blocks

• HW Components
• A simple controller
• socket selection
• control signal generation
• The built-in JTAG unit
• providing access to JTAG signals
  (TMS,TCK,TDI,TDO, etc.)
• e.g. bscan_virtex and cyclone_jtagb components
• One or more IP sockets
• each for one IP block and addressible by its
  socket ID
• Optional additional components (e.g. for on-chip
  debugging to increase the visibility of internal
  states)

FPGA
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IP Socket

• HW Implementation
• scan-chain based, similar to boundary-scan
• built with FPGA logic
• two major components
• the capture/shift register
• capture a new output vector
• obtain a new input vector and send out the
  captured output vector
• the update register
• hold the input vector to the IP block

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JTAG State Diagram
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Evaluation Cycle Synchronization

• One evaluation cycle requires two JTAG scan
  cycles.
• One scan cycle CAPTURE-gtSHIFT-gtUPDATE
• Obtain an input vector (from the PC) and apply
  it to the input ports of the selected IP block
• Capture the current states of the output ports
• Synchronization
• at signal level (after each simulation delta
  cycle)
• at clock-cycle level (for synchronous designs)

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Simulation Environment

• Develop a Java-based Simulation Environment
• HW modeling in Java, similar to JHDL
  (http//www.jhdl.org)
• an event-based simulation kernel
• can run in a mixed simulation-emulation mode
• extendability (an important requirement for our
  work)
• being extended to support simulation of Run-time
  Reconfigurable IP Cores
• Using a standard HDL simulator is possible.
• via C programming interfaces (e.g. PLI, VHPI,
  FLI)
• All commercial products use this approach.

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Mixed Simulation/Emulation
Software Simulation
FPGA
Simulator
Software Simulation Hardware Emulation
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A Case Study

• Synthesize the Verilog code of an AES IP core
  (http//www.opencores.org)
• targeting a Xilinx Virtex-E chip (XCV300PQ240)
• output a technology-specific netlist in EDIF
  format
• used as a netlist-level IP core
• Prepare a design for the Xilinx design flow
• instantiate the AES IP core, incl.
• an IP socket the controller (generated
  automatically by SW)
• pass all design files to the Xilinx ISE tools to
  generate the final bitstream ? bitstream-level
  IP core

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Synthesis Results

• The AES IP block has a quite large number of I/O
  bits.
• 259 for inputs
• 129 for outputs
• In this case we need a long scan-chain for the
  capture/shift register and the update register.

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Performance Comparison

• Compare the results and the performance of three
  different approaches
• SW simulation using our Java logic simulator
• input the EDIF netlist of the AES (netlist-level
  IP core)
• testbench written in Java
• SW simulation using ModelSim
• input a structural VHDL model (converted from
  the EDIF netlist)
• testbench written in VHDL (functionally
  equivalent)
• Co-emulation using the bitstream-level IP core
  FPGA
• testbench written in Java

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Java Testbench for AES
public class aes_cipher_tb public static void
main(String args) Cell c null try //
load cell from an EDIF netlist c
EdifParser.read("aes_cipher.edf") catch
(Exception ex) System.err.println(ex.getMess
age()) System.exit(-1) / Code for HW
emulation goes here. / // create a waveform
tracer SimTableAdapter sta new
SimTableAdapter() // keep trace of all I/O
signals sta.add( c.getPortList() ) // create
the simulator Simulator sim new Simulator()
sim.load( c ) // load the cell
sim.addTraceEventListener( sta ) sim.start( )
// start the simulator / Code for input
generation goes here./ sim.stop() // stop
the simulator // generate a VCD output file
sta.trace2vcd("wave.vcd")
BoardManager bm null // run in simulation or
emulation mode? if (args.length1
args0.equals("-e")) try // create
Jtag chain info JtagChainInfo jci new
JtagChainInfo(new int5) // select the
first device in the chain jci.selectDeviceID(0
) bm new JtagBoardManager(
new VirtexJtagProgrammer( "LPT1",
jci)) // configure the device (optional)
bm.configure("aes_cipher.bit") // register
the cell for emulation bm.register(0x01, c)
// socket_id1 catch (JtagException jex)
System.err.println(jex.getMessage())
System.exit(-1)
Using the same testbench for both simulation mode
and emulation mode in a unified environment.
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Java Testbench for AES
Wire rst c.getWire("RST") Wire clk
c.getWire("CLK") Wire ld c.getWire("LD")
Wire key c.getWire("KEY") Wire plain
c.getWire("TEXT_IN") Wire done
c.getWire("DONE") key.assign( data1 ) //
set the key // run for 500 cycles, 20ns clk
period for (int i0, index0 i lt 500 i)
if (i0) // reset rst.assign('0')
plain.assign( datai ) else
rst.assign('1') if ((i2)
(ld.equal('0') done.equal('1'))) //
load new plaintext plain.assign( dataindex
) index (index1) 4
ld.assign('1') else ld.assign('0')
clk.assign('1') // clk '1' for 10ns
sim.runFor(10.0) clk.assign('0') // clk '0'
for 10ns sim.runFor(10.0)
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Simulation Results
Not include board configuration time
All experiments were done on a notebook (800MHz,
256MB, WinXP).
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Our Test Platforms
APEX20KE EP20K200E
Virtex-E XCV300E
Virtex-II XC2V1500
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Conclusion and Perspectives

• Described a HW/SW infrastructure for
  co-simulation and emulation using JTAG-based
  standard interface
• can be used with different FPGA prototyping
  boards
• Demonstrated the functionality and correctness of
  our prototype implementation using a non-trivial
  case study
• Ongoing Future Work
• extend the simulation environment to support
  co-simulation emulation of static dynamic IP
  cores for FPGA designs
• support other board-specific interfaces (e.g. PCI
  to achieve higher simulation performance)

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The End
Thank you for your attention ?
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