Methods for True EnergyPerformance Optimization

1
Methods for TrueEnergy-Performance Optimization
Dejan Markovic, Prof. Bora Nikolic, Prof. Bob
Brodersen University of California,
Berkeley 2004 BWRC Winter Retreat
2
Energy Constrained Operation
Energy
Echip
increasing gap
Ebattery
Time
Future
Past
Increasing chip complexity and functionality will
overrun available Energy budget
3
Designs Today

• Goal make a design work
• Standard cell-based blocks, unoptimized in terms
  of Energy
• Derived from data rate specification
• Good strategy in the past
• Challenge increasing complexity
• Too much Energy
• New strategy Energy minimization

4
Energy-Area Minimization
?-arch parallel time-mux
Macro Arch.
Energy-Area
Micro Arch.
topology parallel pipeline
Energy
Circuit
W Vth Vdd
Energy
5
Solution Equal Sensitivities
?E SA(??D)
SB?D
(A0,B0)
f (A,B0)
?D
f (A0,B)
f (A1,B)
D0
6
Circuit-Level Adder Example
sizing
dual-VDD
7
Energy-Delay Tradeoff in Adder
66 of energy saved without delay penalty
26 delay improvement without energy penalty
8
ALU Example
Energy-efficient curves in register, adder, and
ALU after performing gate size optimization.
9
Sensitivity
Plots after optimal sizing and change in register
topology (a) Energy of adder and register, (b)
Sensitivity of register, adder, and ALU.
10
Micro-Arch Parallelism Pipelining
A, B adders Input data rate f
Optimal ELk/ESw about 0.5 (All designs operate
at the throughput of the nominal design sized
for minimum delay under Vddmax and Vthref)
11
Optimal Level of Parallelism
Area AP PARef

• Practical rules
• EOppar lt EOpref for T gt Tref(min-EDP)
• Infeasible for T lt Tref(min-EDP)

Parallelism improves Delay and Energy at the
expense of increased Area
12
Time-Mux SVD Example
s1,w1
s2,w2
s3,w3
s4,w4
PE U?
PE U?
PE U?
PE U?
rk4
rk3
rk2
rk1
y

• PE too Fast
• Large Area

PE-U?1
PE-U?2
wasted time
wasted time
PE-U?3
0
Tsymbol
PE-U?4
PE-U?1
PE-U?2
PE-U?3
PE-U?4
s1,w1
s2,w2
Time-Mux Architecutre
PE U?
s3,w3
y

• Some Mux overhead
• Large Area reduction

s4,w4
13
Energy-Area Tradeoff

• Top1 can be achieved with M5 (E lt Eop1) or M3
  (E lt Eop2 )
• Area (M5) 3/5 Area (M3)

Energy-Area is a measure of the overall chip cost