Computer Networks

1
MIPS Instruction Subset

• 6-bit Op-code
• 5-bit register field(s)
• 6-bit funct code/immediate data

2
Hardware Subunits I-fetch

• Instruction Fetch
• Common to R-type, branch and Mem instructions

32
ADD
32
4
32
Instruction Address
PC
32
Instruction
Instruction Memory
3
Hardware Subunits R-type
ALU Operation
Register file
5
3
Read register 1
32
Read data 1
5
Read register 2
Zero
Instruction
ALU
5
Write register
Result
32
Read data 2
Write data
RegWrite
4
Hardware Subunits - Mem
ALU Operation
3
Register file
32
5
MemWrite
Read data 1
Read register 1
Data memory
Zero
5
Read register 2
32
Instruction
ALU
Read data
5
Result
Address
Write register
Read data 2
32
Write data
Write data
RegWrite
MemRead
16
Sign extend
32
5
Hardware Subunits - branch
To PC
32
32
PC 4
0
1
ADD
Shift left 2
PCSource
Instruction
32
16
Sign extend
6
Interconnection I-Fetch R-type
32
ADD
32
ALU Operation
Register file
4
5
3
Read register 1
32
32
Read data 1
Instruction Address
PC
Read register 2
5
Zero
32
Instruction
ALU
5
Write register
Result
Instruction Memory
32
Read data 2
Write data
RegWrite
7
Interconnection Add Mem Reference
ALU Operation
3
Register file
32
5
MemWrite
Read data 1
Read register 1
Data memory
Zero
5
Read register 2
32
Instruction
ALU
Read data
5
Result
Address
Write register
Read data 2
32
Write data
Write data
RegWrite
MemRead
16
Sign extend
32
32
ADD
ALU Operation
32
Register file
4
5
3
Read register 1
32
32
Read data 1
Instruction Address
PC
Read register 2
5
Zero
32
Instruction
ALU
5
Write register
Result
Instruction Memory
32
Read data 2
Write data
RegWrite
8

• Add computation of Effective Address

ALU Operation
3
Register file
MemWrite
Read data 1
Read register 1
Data memory
Zero
Read register 2
Instruction
32
ALU
Read data
Result
Address
Write register
32
Read data 2
Write data
Write data
RegWrite
MemRead
16
32
Sign extend
32
ADD
32
Register file
4
ALU Operation
5
Read register 1
3
32
32
Read data 1
Instruction Address
PC
Read register 2
5
Zero
32
Instruction
ALU
5
Write register
Instruction Memory
Result
32
Read data 2
Write data
RegWrite
32
Sign extend
16
9
ALU Operation
3
Register file
MemWrite
Read data 1
Read register 1
Data memory
Zero
Read register 2
32
Instruction
ALU
Read data
Result
Address
Write register
32
Read data 2
Write data
Write data
RegWrite
MemRead
16
Sign extend
32
32
ADD
32
Register file
ALU Operation
4
3
5
Read register 1
32
32
Read data 1
Instruction Address
PC
Read register 2
5
Zero
32
Instruction
ALU
5
Write register
Result
32
Instruction Memory
Read data 2
0
Write data
1
RegWrite
32
Sign extend
16
ALUSrc
10

• Add Mem write

ALU Operation
3
Register file
MemWrite
Read data 1
Read register 1
Data memory
Zero
Read register 2
32
ALU
Read data
Result
Address
Write register
32
Read data 2
Write data
Write data
RegWrite
MemRead
32
ADD
32
Register file
ALU Operation
4
3
5
Read register 1
32
32
Read data 1
Instruction Address
PC
MemWrite
Read register 2
5
Zero
Data memory
32
Instruction
ALU
Read data
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
Write data
1
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
11

• Add Mem read

ALU Operation
3
Register file
MemWrite
Read data 1
Read register 1
Data memory
Zero
Read register 2
32
ALU
Read data
Result
Address
Write register
32
Read data 2
Write data
Write data
RegWrite
MemRead
32
ADD
32
Register file
ALU Operation
4
3
5
Read register 1
32
32
Read data 1
Instruction Address
PC
MemWrite
5
Read register 2
Zero
Data memory
32
32
Instruction
ALU
Read data
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
Write data
1
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
12
ALU Operation
3
Register file
MemWrite
Read data 1
Read register 1
Data memory
Zero
Read register 2
32
ALU
Read data
Result
Address
Write register
32
Read data 2
Write data
Write data
RegWrite
MemRead
32
ADD
32
Register file
ALU Operation
4
3
5
Read register 1
32
32
Read data 1
Instruction Address
PC
MemWrite
5
Read register 2
Zero
Data memory
32
Instruction
MemToReg
ALU
5
Write register
Result
Address
32
Instruction Memory
Read data 2
32
0
32
Read data
1
Write data
1
0
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
13
i-fetch R-type Mem
32
ADD
32
Register file
ALU Operation
4
3
5
Read register 1
32
Read data 1
32
Instruction Address
PC
MemWrite
Read register 2
5
Zero
Data memory
32
Instruction
MemToReg
ALU
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
32
Read data
1
32
Write data
1
0
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
14
Interconnection Add BEQ
To PC
32
32
PC 4
0
1
ADD
Shift left 2
PCSource
Instruction
16
32
Sign extend
PCSource
32
ADD
Branch
32
Register file
ALU Operation
4
3
5
Read register 1
32
32
Read data 1
Instruction Address
PC
MemWrite
5
Read register 2
Zero
Data memory
32
Instruction
MemToReg
ALU
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
32
Read data
1
32
Write data
1
0
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
15
To PC
32
32
PC 4
0
1
ADD
Shift left 2
PCSource
Instruction
16
32
Sign extend
PCSource
32
ADD
Shift left 2
Branch
32
Register file
4
3
5
Read register 1
ALU Operation
32
32
Read data 1
Instruction Address
PC
MemWrite
5
Read register 2
Zero
Data memory
32
Instruction
MemToReg
ALU
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
32
Read data
1
32
Write data
1
0
RegWrite
Write data
32
Sign extend
MemRead
16
ALUSrc
16
To PC
32
32
PC 4
1
0
1
ADD
PCSource
PCSource
32
ADD
ADD
Shift left 2
Branch
32
Register file
4
3
5
Read register 1
ALU Operation
32
32
Read data 1
Instruction Address
PC
MemWrite
5
Read register 2
Zero
Data memory
32
Instruction
MemToReg
ALU
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
32
Read data
1
32
Write data
1
0
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
17
To PC
32
32
PC 4
1
0
1
ADD
32
0
1
PCSource
32
ADD
ADD
Shift left 2
Branch
32
Register file
4
3
5
Read register 1
ALU Operation
32
32
Read data 1
Instruction Address
PC
MemWrite
5
Read register 2
Zero
Data memory
32
Instruction
MemToReg
ALU
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
32
Read data
1
32
Write data
1
0
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
18
Final Datapath
32
0
1
PCSource
32
ADD
ADD
Shift left 2
Branch
32
Register file
4
3
5
Read register 1
ALU Operation
32
Read data 1
32
Instruction Address
PC
MemWrite
5
Read register 2
Zero
Data memory
32
Instruction
ALU
MemToReg
5
Write register
Result
Address
32
Instruction Memory
Read data 2
0
32
Read data
1
32
Write data
1
0
RegWrite
Write data
Sign extend
MemRead
32
16
ALUSrc
19
Instruction Encoding Add Instruction Bits

• Opcode bits 31-26
• Read register 1 bits 25-21
• Read register 2 bits 20-16
• Immediate bits 15-0

• Write register
• R-type 15-11
• lw 20-16

20
Add Instruction Fields
32
0
1
PCSource
32
ADD
ADD
Shift left 2
Branch
32
Register file
4
Inst25-21
3
Read register 1
ALU Operation
32
Read data 1
32
Instruction Address
PC
Inst20-16
MemWrite
Read register 2
Zero
Data memory
32
MemToReg
Instruction
ALU
?
Write register
Result
Address
32
Instruction Memory
Read data 2
0
32
1
32
Read data
Write data
1
0
RegWrite
Write data
Inst15-0
Sign extend
MemRead
32
16
ALUSrc
21
RegDest
32
0
1
PCSource
32
ADD
ADD
Shift left 2
Branch
32
4
Register file
Inst25-21
3
Read register 1
ALU Operation
32
32
Instruction Address
Read data 1
PC
Inst20-16
MemWrite
Read register 2
Zero
Data memory
Instruction
MemToReg
ALU
0
Write register
Result
Address
32
1
Read data 2
Instruction Memory
0
Inst15-11
32
1
32
Read data
Write data
1
0
RegWrite
Write data
Inst15-0
Sign extend
MemRead
32
16
ALUSrc
22
What are control points in CPU ?

• From final data path

32
0
1
PCSource
32
ADD
ADD
RegDest
Shift left 2
Branch
32
4
Register file
Inst25-21
3
Read register 1
ALU Operation
32
32
Instruction Address
Read data 1
PC
MemWrite
Inst20-16
Read register 2
Zero
Data memory
Instruction
ALU
MemToReg
0
Write register
Result
Address
32
1
Read data 2
Instruction Memory
Inst15-11
0
32
Read data
1
32
Write data
1
0
RegWrite
Write data
Inst15-0
Sign extend
32
MemRead
16
ALUSrc
23
Implementation of CPU Control

• From truth tables of CPU control vs. Op-code

24
RegDest Branch MemRead MemToReg ALUGroup MemWrite
ALUSrc RegWrite
Inst31-26
CPU Control
25
ALU Group

• Four groups according to instruction types
• 00 perform an add for lw, sw (ignore funct
  field)
• 01 perform a sub for beq (ignore funct field)
• 11 perform or for ori (ignore funct field)
• 10 ALU op is determined from funct field
  R-type instructions

26

• What ALU control is required for each instruction
  ?

27

• Given 6-bit function bits,
• ALU operation is determined by
• 6-bit function bits and
• ALU group

Zero
ALU
Result
3
ALU control
Inst5-0
2
ALUGroup
28
CPU Control
0
32
1
RegDest Branch MemRead MemToReg ALUGroup MemWrite
ALUSrc RegWrite
Inst31-26
CPU Control
PCSource
32
ADD
ADD
Shift left 2
32
Register file
4
Inst25-21
Read register 1
Read data 1
Instruction Address
PC
Inst20-16
Read register 2
Zero
Instruction
ALU
Data memory
0
Write register
Result
Address
Instruction Memory
Read data 2
1
0
32
ALU Operation
Write data
Read data
1
Inst15-11
3
1
Write data
0
Sign extend
32
Inst15-0
16
ALU control
Inst5-0
2
29
Datapath for R-type Instructions
0
PC431-28
1
RegDest Branch MemRead MemToReg ALUGroup MemWrite
ALUSrc RegWrite
Inst31-26
CPU Control
PCSource
32
ADD
ADD
Shift left 2
32
Register file
4
Inst25-21
Read register 1
Read data 1
Instruction Address
PC
Inst20-16
Read register 2
Zero
Data memory
Instruction
ALU
0
Write register
Result
Address
Instruction Memory
Read data 2
1
0
32
Read data
1
Inst15-11
Write data
3
ALU Operation
1
0
Write data
Sign extend
32
Inst15-0
16
ALU control
Inst5-0
2