VLSI Design Flow

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VLSI Design Flow

• Samiha Mourad

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Design Methodologies

• Architecture suitable for VLSI that facilitates
  debugging, testing and maintenance

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Design Attributes

• Cost
• Speed
• Power
• Performance power x speed
• Time to Market
• Testability

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Synthesis
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Design Flow

• Logic Design
• Physical Design
• Wafer to Fab

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From Specs to Netlist
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Physical Design
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Design Methodologies
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CAD Tools

• All aspect of ASIC design depends on CAD
  tools
• Software program that perform different
  tasksDesign entry, verification and simulation,
  Synthesis, layout
• Most these problems are NP-complete
• There is a need for algorithms that utilize
  some heuristic and a cost function to stop the
  computation.

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Semi-custom

• Fully Custom Hand crafted transistors. Most
  flexible approach. Compact design. Long time to
  market. Suitable for large volume Memory and
  Microprocessors
• Semi-Custom Use of pre-designed cells and CAD
  tools. Restrictive. Less compact. Lower
  performance. Shorter time to market. Moderate
  volume.
• Standard cells
• Gate arrays
• Programmable
• ROM, PLA, PLD
• FPGA

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Core-Based
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Semicustom Design
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Standard Cells

• Layout of common cells
• NAND, NOR, AOI
• Fixed height
• Placement and Routing
• Internal connections in M1
• Each I/O has a dedicated track
• Channels of variable width

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Gate Arrays

• Patterning M1 interconnects on a Prefabricated
  wafer
• cells (group of transistors)
• Macros occupy one of
• more neighboring cells
• Channels of variable width

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Programmable Logic

• AND/OR
• ROM Fixed AND, programmable OR
• PLA Both planes are programmable
• PLD Programmable OR, fixed AND
• Gate Arrays
• Regular blocks of random logic cells
• Fixed width channels or
• no channels sea of gates
• Segmented tracks
• Programming device RAM, Antifuse

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Gate Arrays Arrangements
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Pin Inductance
Samiha Mourad 1997
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Comparison
Fully
Custom
Performance and Cost
Cell-
based
Gate
Array
FPGA
Time to Market
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Floor Planning Perspective
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Physical DesignPlacement and Routing

• Given a netlist describing the interconnections
  of the logic blocks and design rules, it is
  required to find
• 1. Locations for the logic blocks (Placement)
• 2. Paths for all interconnections between
• blocks (Routing)

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Placement Routing

• Initial placement
• Random placement
• Global routing
• Iterative improvement
• Pairwise exchange
• Detailed routing
• Switch box routing
• Channel routing

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Graph Theory

• G(V ,E, w)
• V set of vertices, nodes
• objects, gates, locations
• E set of edges
• Eij a relation between Ei and Ej
• Interconnect between 2 gates
• w set of weight for the edges
• length of the edge (cost)
• Directed and non-directed graph
• Cost function a function on W

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Definitions

• Collections of modules M m1, m2, , mn
• with certain attributes, ports, orientations,
  boundaries, heights, etc
• ? Locations to hold the modules L L1, L2, ,
  Lp
• p gt n
• ? Interconnected with signal nets S S1, S2, ,
  Sm
• Use of heuristics to place the modules in the
  locations while optimizing a cost function under
  some constraints.

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Placement
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Algorithms

• A recipe to solve a problem
• Cormen
• Any well defined computational procedure that
  takes some value, or set of values, as input and
  produces some value, or set of values, as
  output.
• It is not a proof
• The solution is valid most of the time
• Must be executed in reasonable time

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Algorithms

• A recipe for solving a problem on a graph
  partitioning, placement, routing, test pattern
  generation, simulation, etc.
• Easily Translated in a programming language
• Execution time is dependent on N, the cardinality
  of the graph vertices set
• Of(N). Loosely speaking, if f cannot be
  represented by a polynomial, the problem is
  called NP-complete Difficult to solve.

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Complexity

• n gt p no solution
• n p n!
• n lt p
• NP-complete problem
• Need for a heuristic and cost function

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Constructive Placement

• Paradigm
• Min-Cut

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Placement
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Channel Terminology
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Global Routing

• A net is a collection of pins connect
  electrically
• Nodes pins
• Edges interconnect
• Weight length measured in horizontal units
• Network is complete graph
• Form Minimum Spanning Tree MST
• Repeat until all nodes are in MST
• Select min cost edge gtgt MST
• Select the min cost edge from all edges connected
  to nodes in MST, place in MST

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Channel Routing

• Left Edge Algorithm
• C set of connections Ci left( i ) coordinate of
  Ci
• Sort Ci in order of left ( i )
• Assign the first connection to the first
  horizontal track and delete it from C.
• Repeat until C is empty Find the next net in C
  such that
• left( i1) is to the right Ci. If the track is
  full, go to the next track. Delete Ci1 from C.
• Works if the constraint graph does not have
  loops.

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Channel Routing

• The constraint graph indicates the relative
  positions of the nets. b has to be on a track
  above d and c. Also, d is above a. Since left
  of d is to the right of c, then d can be on the
  same track. In this case, there are more tracks
  so we can put it on a separate one. However we
  need to pack the track. a should be below d.

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Channel Routing

• Left Edge Algorithm does not work since a has to
  be below d and d below a.
• doglegs are used thus using more vertical
  tracks than necessary.

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Maze Routing
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Maze Routing
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Routing Constraints
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Back Annotation
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Pin Inductance
Samiha Mourad 1997