EGE535 Low Power VLSI Design

1
EGE535 Low Power VLSI Design

•  
• Lecture 2
• MOSFET Basics

2
Intrinsic and extrinsic Semiconductors
Intrinsic semiconductor (no carriers at 00 K)
Intrinsic semiconductor (ni pi at room temp )
N type semiconductor (ni gtgt pi at room temp)
N type semiconductor (ni gtgt pi at room temp)
P type semiconductor (pi gtgt ni at room temp)
3
PN Junction
P-
N
N type semiconductor (ni gtgt pi at room temp)
P type semiconductor (pi gtgt ni at room temp)
P
N
Depletion Region
P-N Junction
4
PN Junction Reverse Biasing
Depletion width increases
Reverse bias
5
nMOSFET
6
pMOSFET
7
Objective to have current flow
between Source and Drain
If this can be achieved !

Vds

Vds
Ids
Ids
Gate
Gate
Drain
Drain
Source
Source


























L



























































































P-











P-








8
NMOS Transistor
9
Capacitor Charging
10
The MOS Capacitor
11
The MOS Capacitor

12
The MOS Capacitor
13
Threshold Voltage Vth
Vgs
14
Strong Inversion
15
Threshold Voltage Vth
Much More Positive
More Positive
Less Positive
Weak Inversion
Moderate inversion
Strong inversion
n ? Ions V Vth
n gtgt Ions V gtgt Vth
nltlt Ions V lt Vth
Vth Minimum Voltage for Inversion
16
Cutoff Ids 0
17
First Approximation Threshold Voltage
Vgs
lt Vth
Vgs
gt Vth
Gate
Gate
Source
Drain
Source
Drain


























L

L
















































































p-





p-


































Plenty of surface electrons
No surface electrons
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Surface Charge with Vgs
Vgs
gt gtVth
Vgs
gt Vth
Gate
Gate
Source
Drain
Source
Drain
























L










L





































































p-














p-





























Enough electrons
Much More electrons
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Cutoff Ids 0
Vds 0
gt Vth
Vgs
Ids 0
Gate
Source
Drain













L










































p-


















20
Linear Idsincreases with Vds
Vdslt lt Vgs-Vth
Vgs gt Vth
Ids gt 0
Gate
Source
Drain



L










































p-















21
Example
Vth 0.8V
Vds
Ids Linear
Resistive region
1V
Vgs
Ids gt 0
2V
Drain
Source
2V
1.5
1
1.8
1.3




0 .2 .5 .7 1V













































P-







S
D
0 .2 .5 .7 1V
22
Pinch Off Vds Vgs-Vth
Vgd Vgs (Vgs Vth ) Vth
Vds Vgs Vth
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Saturation Ids independent of Vds
Vds gt Vgs-Vth
Ids sat
Vgs gt Vth
Source
Drain






















































p-silicon





























Pinch Off extends No channel !!
Ids Saturation
Ids
For VdsgtVgs-Vth
Vds Vgs-Vth
Velocity saturation Ids constant
Vds
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Regions of Transistor Operation
1. Linear region VGS gt Vth VDS lt VGS Vth
Vth - threshold voltage 2. Saturation
region VGS gt Vth VDS ? VGS - Vth
Deep Triode
Triode
 
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Current Equation
26
Channel Length Modulation
gt Vgs-Vth
Ids
gt Vth
Source
Drain






















































p-silicon





























Pinch Off extends channel length reduces
Ids Saturation
Ids
Vds
-VA
0.005 ? ? ? 0.02V-1
27
PMOSFET
28
PMOSFET No current
Vds 0
Vgs gt Vth
Ids 0
_

Gate
Drain
Source



L















N-



Vth Negative voltage
Vds Negative voltage
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PMOSFET Current flow
Vds gt 0
Vgs gt Vth
Ids gt 0
_

Gate
Drain
Source



L















N-



Vgs Vds Negative voltages
30
PMOS Transistor

• Linear region VGS gt Vth
• Vth - threshold voltage (Min for inversion
  layer)
• VDS ltlt VGS Vth
• VDS lt VGS Vth
• 2. Saturation region VGS gt Vth
• VDS ? VGS - Vth

Deep Triode
Triode
 
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MOSFET Symbols