Spatially Distributed 3D Circuit Models

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Spatially Distributed3D Circuit Models

• Michael Beattie Electronic Design Automation
• Hui Zheng Austin Research Lab
• Anirudh Devgan Austin Research Lab
• Byron Krauter Electronic Design Automation
• IBM Corporation Austin, Texas

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Background

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Conventional BEM Extraction

• Starts with dense potential matrices with spatial
  information
• Vector potential integrals for inductance
  extraction
• Scalar potentials for capacitance extraction
• Solves for net behavior (net capacitance loop
  inductance) while strictly obeying Kirchhoffs
  laws static behavior
• Produces small dense models
• Loses spatial information

Capacitance Extraction
Inductance Extraction
0 V
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Inverse Inductance Extraction

• Differs from conventional BEM extractionby
  generating segment, not net properties
• Starts with dense partial inductance matrices
• Inverts truncates matrices irrespective of net
  KCL
• Equivalent to applying loop potentials across
  segment lengths
• Easily truncated as L-1 drops off fast due to
  shielding effects
• Produces large, sparse models with spatial
  information

0 V
Inverse Inductance Extraction Loop Potentials
for Single Segment Extraction
1 V
0 V
0 V
0 V
0 V
0 V
0 V
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Distributed BEM Capacitance Extraction

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Distributed BEM Capacitance Extraction

• Similar to inverse inductance extraction
• Derives segment, not net couplings
• Violates static conditions by considering
  discontinuous surface potentials
• Windowed extraction
• Highly parallelizable
• Produces spatially distributed coupling models
• segment-to-segment couplings
• no distribution heuristics

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Distributed Extraction not likeRegular BEM
Capacitance Extraction

• Discontinuous surface potentials(ground all but
  one segment)
• Locally solve for each segment
• Coarse panels are sufficient for remote segments
• Yields spatially distributed C model with self
  coupling terms
• Segment length depends on time step / accuracy

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Spatially Distributed 3D Circuit Models

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Spatially Distributed 3D Circuit Models

• Two step discretization process
• Segment lengthsbased on circuit speeds
• Segment panel / filament sizesbased on
  extraction accuracy
• Power planes require separate Lx , Ly C
  segments
• Extract for all segments
• Inverse inductances
• Distributed segment capacitance
• Combine netlists simulate
• Skin effect can be modeled with RL-1 Foster
  filters

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Simulation Efficiency

• Sparse L-1 matrix densities is less thanfor
  comparable sparse partial inductance modelsfor
  similar simulation accuracy
• Linear circuits can be solved via nodal analysis
  when using only L-1 models and current sources
• Nodal analysis circuit equations are symmetric
  positive definite
• These equations can be solvedvia more efficient
  Cholesky factorization

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L-1 based Transient Simulation

• Inner-loop Linear System (BE)
• Clock tree/mesh with 1.8 million elements(no
  couplings)

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Adaptive Gridding

• Extract coupling from specific central segmentto
  all segments within a given distance (window)
• Discretize surfaces of segments finer, the closer
  they are to the central segment (adaptive
  gridding)
• Small impact on accuracy due to shielding
• Faster extraction compared to uniform gridding

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How L-1 Differs from Capacitance

• Conductors split into segments for simulation
  accuracy
• Segments in turn split into panels for extraction
  accuracy
• BEM capacitance extraction coalesces
  charges(non-directionally)
• C AT(P) -1 A
• Capacitance matrix is diagonally dominantwith
  negative off-diagonals
• Proof based on all surface potentials being 1 or
  0 Volts,Gauss Law harmonic functions being
  extreme at their boundaries

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Serial and Parallel Filaments

• Inductance filaments have a direction circuit
  topology
• L-1 coalescing differentiates between parallel
  (admittance) and serial (impedance) filaments
• L-1 (AsT(ApT(L) -1 Ap)-1As)-1
• L-1 not always diagonally dominantand can have
  positive off-diagonals
• Diagonal dominance proof used for C breaks down
  because vector potentials on surface are not 1 or
  0,but length integrals of vector potential are 1
  or 0

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High-Frequency L-1 Models

• Use Foster RL-1 filters to modelimpedance
  frequency dependence
• Model skin effect in individual segments

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Signal Integrity Analysis

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Chip / Board Approximation

• Common all power supplies add chip board
  planes to allegro extract file
• Initial Shapes Processing
• merge eliminate overlapping shapes
• discretize lines planes
• create node numbers
• prune out smallest shapes

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Signal Integrity Flow
pin-to-node correlation data
layout data
shape process
shapes data
technology data
shape-to-node correlation data
sparse L-1 C matrices
block process
full package extract neighbor list build
blocks for parallel extraction
neighborlist
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Signal Integrity Flow (contd)
neighbor list
sparse L-1 C matrices
channel shapes processing
netlist build
linear simulation
signal integrity channels for parallel simulation
results
chip, board, analysis reporting instructions
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Boundary Conditions

• - Linear analysis with 50 W Norton driver models
• - All chip supplies shorted all board supplies
  shorted
• - Near and far end termination with Zo50 W
• - Single point ground model -gt local
  differential measurements
• Apply
• Saturated ramp to find far end and saturated near
  end noise
• Triangular pulse to create time domain scattering
  models

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Sample Signal Integrity Analysis

• Allegro Layout (Victim Net Highlighted)

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Layers Above / Below
Layer Above
Layer Below
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Discretized Ground Planes
Shapes All Levels Displayed
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Near / Far End Noise
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TDR Measurement / Simulation
1 Volt ramps with 40 ps rise time
In simulation, transmission lines are modeledas
equivalent L-1 C networks.
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Measured Differential TDR
From this data the Differential transmission
line characteristic impedance is from 92 Ohms to
108 Ohms.
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Simulated Differential TDR
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Calibration to 2D Analysis
PATS Layout
EIP Cross Section
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Comparison with EIP

• EIP PATS Units
• C11 1.3770 1.3887 pF/cm
• C12 0.2313 0.2217 pF/cm
• L11 2.910 3.262 nH/cm
• L12 0.488 0.548 nH/cm
• Z0 46.0 48.5 Ohms
• td 63.3 66.1 ps/cm

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Near / Far End Responses
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Summary

• Inverse Inductance allows for very efficient
  modeling and simulation of complex 3d
  interconnect
• Segment-to-segment capacitance captures spatial
  distribution more accurately than net-by-net
  models
• L-1 and C similar, but fundamental
  differencesdue to KCL and directionality of
  magnetic field
• Segment-based capacitance and inverse inductance
  interconnect models allow for windowed extraction
  and huge speed-ups through extract
  parallelization
• Signal integrity analysis parallelizablethrough
  channel modeling