Integrated Circuit Engineering

1
Integrated Circuit Engineering K.Y.Tong (Rm
DE610) References 1. Richard C.Jaeger,
Introduction to Microelectronic Fabrication,
Prentice Hall, 2002, 2nd Edition. 2. S.M.Sze,
VLSI Technology, McGraw Hill, 2nd Edition
3.Stephen A.Campbell, The Science and
Engineering of Microelectronic Fabrication,
2001, Oxford
2

• 1. Development of Integrated Circuits
• The advent of revolution in electronics made
  possible by the development of higher
  integration of density of silicon integrated
  circuits, e.g. memories of 512M
• Advantages of increased density of integration
  - reducing system
  cost (IC cost mainly in packages),
• enhancing overall system function, and
• increasing reliability.
• Requires tremendous research in several
  areas semiconductor device physics,
  fabrication technology and computer-aided-design
  tools.

3

• Increasing integration density on the wafer is
  achieved by shrinking the dimensions of the
  semiconductor device. Small geometry
  transistors also have much faster speed.

• In MOS IC, the channel length of the MOSFET has
  been continuously decreased from an initial
  value of 10 ?m to deep sub-micron (0.15?m) in
  the present manufacturing state of the art. In
  research labs, devices based on nanotechnology
  (90 nm and less) are built.
• Must understand clearly the physics of small
  geometry devices in order to design MOSFET in
  VLSI, which are very different from long channel
  devices.

4
(No Transcript)
5

• To fabricate small geometry devices requires
  the definition of very fine patterns on the wafer
  during the photolithographic process. Other
  physical problems in small size structures urges
  the development of new fabrication process, such
  as photolithography, plasma etching .
• The fabrication environment has also become
  more stringent because of the yield problem in
  large area wafers. Class 10 or even lower clean
  room has to be used to control the amount of dust
  particles.

6

• Finally given the capability to fabricate high
  density integrated circuits, we must be able to
  design the circuit itself starting from the
  system specifications. The design of a circuit
  with millions of transistors (including logic,
  circuit and mask layout design) is only possible
  with the use of computer-aided-design tools on
  workstations. This is an area where computer
  science plays an important role in the
  development of integrated circuits.

7

• 1.1 Monolithic and Hybrid Circuits
• ICs that are placed entirely on a single chip
  of semiconductor (usually Si) are called
  monolithic circuits. Monolithic circuits have
  the advantage that mass production by batch
  processing is possible.

• A hybrid circuit contains one or more monolithic
  circuits or individual transistors bonded to an
  insulating substrate with other resistors,
  capacitors and interconnections. Hybrid circuits
  allow the use of more precise resistors and
  capacitors, and are less expensive to build in
  small numbers.

8
1.2 Fabrication of monolithic circuits simple
review

• The basic idea behind the fabrication process is
  to selectively dope certain regions of the
  semiconductor to form p-n junctions, and then
  interconnect the doped regions to form devices
  and circuits.
• Since SiO2 is a good barrier to most dopant
  impurities, selective doping is done through
  windows opened in a thermal grown oxide layer
  using photolithographic techniques. By exposing
  the photoresist coated on the wafer through a
  glass mask to UV light, the desired pattern can
  be developed on the photoresist, and then
  transferred to the oxide layer.

9
UV
Mask PR SiO2 Si
n
n
10
Al
SiO2
p
p
n
11
Main fabrication processes include i) oxidation
(field oxide, and gate oxide in MOSFET), ii)
diffusion, ion implantation for doping
impurities, iii) photolithographic process for
defining pattern, iv) etching of insulator,
metal, or Si by chemical solution or plasma,
v) deposition of polycrystalline Si , silicon
oxide, silicon nitride by chemical vapour
deposition (CVD), vi) deposition of
metallization layer by thermal or electron
beam evaporation, and sputtering.
12
Environment i) the particles in a clean room
are controlled using HEPA (high efficiency
particulate air) filters, and slightly
pressurized. Particle counts are given in units
of particles of 0.5?m size per cu.ft. ii) water
used must be deionized to remove ions, with a
resistively of 12-18 M?. Chemical solutions
have to be of pure semiconductor grade. iii)
personnel working in clean room must be properly
dressed to avoid bringing in particles.
13
2. Incorporation and Diffusion of Impurities

• Impurities can be doped into a semiconductor to
  form a p-n junction by thermal diffusion and ion
  implantation. Diffusion of dopant impurities in
  selected regions can be carried out through
  windows in a SiO2 masking layer at high
  temperature in a furnace.

• Dopant incorporation by diffusion takes place at
  high temperatures 1000oC in a furnace usually
  involves two processes pre-deposition followed
  by drive-in.
• Pre-deposition is a process where the wafer
  surface is in contact with a fixed concentration
  of the dopant source. Three different ways are
  possible

14
i) passing a dopant gas through the furnace, ii)
bubbling a carrier gas through a solution
containing the dopants to produce a stream
saturated with the dopant, iii) bonding a solid
source of doped oxide layer onto the wafer by
spin-on technique.
N2
To furnace
Solid dopant film
Si
dopant
Temp Control Bath
15

• During pre-deposition, the required amount of
  dopant diffuses into the semiconductor. In the
  drive-in process, the semiconductor is heated in
  an inert environment to cause a redistribution of
  the pre-deposited dopant to a desired profile.

S21

• Ion implantation is particularly useful in
  forming shallow junctions with high doping
  concentrations. Ionized-projectile atoms are
  introduced into solid targets with enough kinetic
  energy (3 to 500keV) to penetrate beyond the
  surface regions (from 100? to ?m). A gas source
  of the dopant such as BF3 or AsH3 is energized at
  a high potential to produce an ion plasma. The
  analyzer magnet then selects only the desired ion
  species , which is accelerated to a high
  velocity.

16
2.1 Diffusion theory of impurities Lattice
atoms in a solid vibrate randomly about their
mean positions, and there are chances that
vacancy or interstitial defects occur in the
crystal at increased temperature. Diffusion
takes place when an impurity atom migrates to the
vacancy or interstitial defect.
Host atom
Vacancy defect
17
Interstitial vacancy
Host atom
movie
The flux of atoms (number passing through unit
area per sec) J in solid can be given by Fick's
law where D is the diffusion coefficient
and C is the concentration.
S32
18

• For an intrinsic material, the diffusivity is
  given by
• Do is the preexponential factor dependent on the
  vibrational frequency of atoms in lattice or
  interstitial sites and EB is the binding energy
  of the site.
• Under high dopant concentrations, the diffusion
  coefficient D varies with the concentration. For
  example in arsenic, D is proportional to the
  concentration.

19

• 2.2 Dopant Incorporation
• Doping by thermal diffusion involves two
  processes pre-deposition and drive-in.
• Pre-deposition is a diffusion process with
  constant impurity
• surface concentration
• Drive-in is a process with constant total amount
  of dopant.
• Continuity of diffusion gives (Fick's 2nd law)

20
In the following, the above diffusion equ. is
solved using a constant D approximation. i)
For constant surface concentration during
pre-deposition, the boundary condition at the
surface is C(o,t)Cs where Cs is the
saturation concentration. Far away from the
surface, the dopant concentration is zero, i.e.
C(?,t)0. Also, there are no dopant in the solid
initially, i.e.. C(x,0)0. The solution of the
diffusion equation with the initial and boundary
condition is
21
ii) For drive-in with constant total dopant, the
boundary condition is where Qo is the total
amount of dopant initially present as a result of
pre-deposition. By approximating the
pre-deposited profile as a delta function, the
solution of the diffusion equ. is then given by a
Gaussian distribution as The amount Qo can
be found from the pre-deposition process
as where the subscript 1 is for
predeposition values.
22
after pre-deposition
Dopant concentration
after drive in
x
xj
23
The junction depth xj is defined as the position
where the doping concentration is equal to the
background impurity concentration. Assuming the
diffusivity is independent of the impurity
concentration, the sheet resistance Rs
(resistance per unit square) of the doped region
can be shown to be related to the doping profile
C(x) as Average resistivity is defined as

24
Resistance R Rs L/W
W
x0
L
dx
current
xj
25

• 2.4 Ion Implantation
• Introduction of a dopant into a semiconductor by
  ion implantation involves penetration of
  accelerated ions into the solid. As ions
  penetrate the solid, the ions lose their energy
  by collisions with the electrons and nuclei of
  the host material and come to rest.
• Electron stopping is the transfer of ion
  energy to the "sea" of electrons in the solid
  with the generation of electron-hole pairs. The
  energy loss is similar to moving through a fluid,
  and is proportional to velocity of ions.

26

• Energy loss per unit length due to electron
  stopping is called Se.

• Nuclear stopping involves ion-nucleus
  interaction, either displacing nuclei or
  transferring energy to the lattice by electric
  force interaction. Slowly moving ions are more
  strongly scattered by these events, and so energy
  loss increases with lower velocity and higher
  mass. Energy loss per unit length due to nuclear
  stopping is called Sn.

27
If electronic and nuclear stopping are
independent, the average range of penetration Rp
of ions of energy Eo is obtained as Due to
random scattering, the distribution of implanted
dopants will have an average projected range Rp
with a standard deviation ?Rp in a symmetric
Gaussian distribution used to approximate the
profile (called the LSS theory). Suppose the
total number of dopants implanted per unit
surface area is Ni, and the concentration of
dopants at a distance x from the surface is
C(x).
28
Ni is measured by the current registered by a
charge integrator connected to a metal conductor
in good contact with the wafer.
where I is the beam current applied for time t, A
is the aperture area, and m is the charge
number(e.g. 1 for singly ionized ion).
29
Most semiconductors are crystalline and have
highly anisotropic properties. Because of the
ordered arrangement of lattice atoms, ions can
penetrate more deeply into the crystal along
major axis and planes. This phenomenon is called
channeling effect. To avoid channeling, ion
implantation is often carried out with an ion
beam misoriented from the major axis by an angle
of at least 7 to 10?. Both Si and GaAs behave
nearly as an amorphous solid when a misoriented
beam is used.
channeling
30
Implantation damage and annealing As ions are
bombarded into the crystal, atoms can be
displaced from their lattice sites. This
displacement leads to the creation of vacancies
and interstitial atoms, known as Frenkel defects,
as well as complex lattice defects along the ion
path (clusters). The damaged areas begin to
overlap with increasing dose, and finally form an
amorphous layer extending to a certain depth.
Such damage is more severe for larger ions,
higher doses, and higher energies. Such damage
can reduce significantly the lifetime of charge
carriers, and must be removed by annealing, where
displaced atoms are allowed to regain their
proper position in the crystal by heating the
semiconductor.
S18
31
Annealing is also required to bring the implanted
ions into substitutional sites in the lattice, so
that they become electrically active. Implanted
ions rarely enter substitutional sites
spontaneously, and implantation without annealing
has little doping effect. In conventional
annealing, the substrates are heated in a furnace
for 15-30 min. In Si amorphous layers disappear
and most implanted dopant is activated at 600?C.
As device dimension and junction depth decrease,
it has become necessary to activate the implanted
ions in such a way that the implanted ions do not
diffuse during annealing using the Rapid Thermal
Annealing (RTA) technique.
32
The distance S atoms travel by diffusion is given
approximately as
The temperature must be high enough to activate
the electrically inactive ions, but the time for
redistribution must be minimized.
33
3. Thermal oxidation The growth of a thin layer
of silicon dioxide on a silicon wafer is an
important feature of planar technology. The
thermal oxide can be used as a mask against
diffusion (field oxide), or as an insulator at
the gate in MOS devices. Thermal oxidation
takes place when Si reacts with dry oxygen or
oxygen carried in water vapour in a furnace.
Si O2 ? SiO2
gate oxide Si
2H2O ? SiO2 2H2 field oxide
34
3.1 Kinetics of oxide growth A simple model of
oxide growth is as follows
Reaction F3
CG
xo
CS
CO
oxide
gas
silicon
Transportation F1
Diffusion F2
Ci
x
35

• For oxidizing species to reach the silicon
  surface, it must go through 3 steps
• i) transportation from gas bulk to the oxide
  interface,
• ii) diffusion across the oxide layer already
  formed,
• iii) reaction at the silicon surface

• In the steady state, the three fluxes (in no. of
  molecules per unit time) corresponding to the
  above steps must be equal. The flux F1 from the
  bulk of the gas to the oxide-gas interface is
• where CG is the concentration of the oxidant in
  the bulk of the gas and CS is the concentration
  of the oxidant right next to the oxide surface,
  hG is the mass-transfer coefficient

36

• To relate the equilibrium oxidizing species
  concentration in the oxide to that in the gas
  phase, we invoke Henry's law. If Co is the
  equilibrium concentration in the oxide at the
  outer surface, C is the equilibrium bulk
  concentration in the oxide, then
• where h is the gas-phase mass-transfer
  coefficient in terms of concentrations in the
  solid.

• The flux F2 of oxidizing species across the
  oxide is given by Fick's law as
• where D is the diffusion coefficient, Ci is the
  oxidizing species concentration in the oxide
  adjacent to the oxide-silicon interface, and xo
  is the oxide thickness.

37

• Assume the flux corresponding to the Si-SiO2
  reaction is proportional to Ci
• where ks is the rate constant of chemical surface
  reaction for silicon oxidation.
• After setting the above three fluxes equal, and
  solving the equs, expressions for Ci and Co can
  be obtained. When the diffusion coefficient is
  very small, Ci ?0 and Co?C. This case is called
  the diffusion-controlled case. In the second
  limiting case when D is very large, CiCo. This
  is called the reaction-controlled case, because
  abundant supply of oxidant is provided at the
  Si-oxide interface, and the oxidation rate is
  controlled by the reaction rate constant and Ci.
  

38

• To calculate the rate of oxide growth, we define
  N1 as the no. of oxidant molecules incorporated
  into a unit volume of the oxide layer. Combining
  above equs, and assuming an initial oxide
  thickness xi at t0 , we can have the following

39
? represents a shift in the time coordinate to
account for the presence of the initial oxide
layer xi. Solving xo gives One limiting
case for long oxidation time gives a parabolic
relationship (diffusion-controlled case)
The other limiting case for short oxidation
time when (t?)??A2/4B gives a linear
relationship (reaction-controlled
case) where B/A is the linear rate
constant.
40

• 3.2 Implications of the oxidation mechanism

• Dry oxidation - Slow, good quality, used for
  thin gate insulator of MOSFET
• Wet oxidation - fast, used for thick field oxide
  (masking against diffusion impurities)

• The growth rate depends on the Si crystal
  orientation. A 111 substrate gives a higher
  growth rate than a 100 substrate because more
  Si-Si bonds are available.

41

• Local oxidation in selected areas is often
  required in IC fabrication, for example as
  isolation regions between adjacent transistors in
  a MOS process. An effective masking material is
  the silicon nitride deposited on top of the
  oxide layer. Silicon nitride can stop the passage
  of oxygen so that oxidation is forbidden under
  the nitride. Selective oxidation is complicated
  by a phenomenon called "bird's peak". It is
  because Si is consumed during oxidation,
  resulting in a movement of the Si-SiO2 interface
  inward. A transitional "bird's peak region"
  exists between the oxidized region and unoxidized
  region as shown below

42
(No Transcript)
43
4. Chemical vapour Deposition Chemical vapour
deposition (CVD) is a process where a film is
formed by chemical reaction of gases at the
wafer surface. Common CVD processes include
deposition of polysilicon, silicon dioxide,
silicon nitride, and epitaxial growth.
4.1 Kinetics of CVD The steps involved in a
CVD process include (i) diffusion of reactant
molecules through the gas to the reaction
surface, (ii) chemical reaction under desirable
conditions such as pressure, temperature, (iii)
diffusion away of by-products.
44
wafer loading cap
resistance heater
wafers
exhaust to pump
gas inlet
45
The following fig. shows the movement of a fluid
past a solid surface, which shows the formation
of a boundary layer.
Fluid
?
46

There is a slowly moving layer of fluid, called
the boundary layer, close to the surface. The
flux of reactant F1 reaching the surface by
diffusing through the boundary layer is
thus where D is the diffusion coefficient
of the reactant in the gas, ? is the boundary
layer thickness, and CG, CS are the
concentrations at the top of the boundary layer
and next to the surface. In practice, the
diffusion of reactants is also affected by the
strong temperature gradient in CVD systems.
47
The flux consumed by reaction at the surface is
given by EA
is the activation energy. We can find the flux by
setting F1F2. Noting that the film growth rate
r is equal to the flux divided by the no. of
atoms per unit volume in the film ?, the value of
r is equal to
48
This equation shows the film growth rate
increases with the concentration of reactants in
the gas. This is only true at low
concentrations, due to the presence of reversible
reactions and other competing reactions. For
example, in the epitaxial growth of Si another
reversible reaction etching the Si surface also
takes place If the concentration of SiCl4
is very high, etching of Si occurs instead of
growth as shown in following fig.
49
Growth
Film growth rate
Mole fraction of SiCl4
Etching
50

• 4.2 Practical CVD systems
• A CVD reactor must serve two purposes provide
  uniform supply of gaseous reactant to the
  surface, and provide enough energy to supply the
  activation energy for the reaction.

• By running the CVD process at reduced pressure
  (LPCVD), a better uniformity of film thickness is
  obtained. The reason is due to the enhancement
  of diffusion of reactant atoms to the surface.
  If the rate of mass transfer is high, the
  deposition is more likely to be controlled by
  surface-kinetics, and yield better uniformity.
  Another reason is the flow stability afforded by
  the low pressure.

51
Silicon dioxide CVD oxide is deposited when
oxidation by thermal growth is not possible due
to the need of a low temperature process, e.g. on
metallised substrates. The most common process is
the oxidation of silane The reaction is
carried out at 400-500?C. CVD oxide contains
significant impurities from the reaction
environment (mainly hydrogen for silane). The
film is also non-stochiometric (usually Si rich)
and is porous. Densification by annealing
creates a film more similar to thermal oxide.
52
Silicon nitride Silicon nitride is used as a
mask for selective oxidation. It is usually
deposited by reaction of ammonia with a
silicon-containing gas at 700-900?C. Silicon
nitride is a good insulator and barrier against
alkali metal contamination. It is thus a good
passivation material for finished devices.
Polycrystalline Silicon Silicon can be
deposited in polycrystalline form, and can be
doped to a low resistively. It is often used for
the gate of a MOSFET, and as a interconnect
link. Polysilicon can be formed by pyrolysis of
silane at temperature of 600-650?C
53

• Vapour phase epitaxy Epitaxy means depositing a
  layer of material without terminating the
  single-crystal structure of the substrate. The
  epitaxial layer can be doped to any
  concentrations irrespective of the impurity
  doping in the substrate. Common gases used
  include SiH4, SiCl4,SiH2,Cl2. Because each
  deposited atom must take its proper place in the
  crystal structure, successful epitaxy requires
  great care
• the surface must be atomically clean before
  deposition,
• the growth rate slow enough that each atom can
  move into the proper location
• high temperatures needed to allow good mobility
  of deposited atoms on the surface (1000-1200?C).
  

54
5. Plasma Etching Etching of various types of
insulator and metal films is necessary to define
patterns in IC fabrication. Wet etching by
chemical solution is simple, but it limits the
minimum dimensions achievable in a device.
Because of the undercutting inherent in isotropic
etching, wet-etched linewidths must be several
times the film thickness. Therefore sub-micron
dimensions cannot be achieved with wet etching,
and plasma etching must be used.
photoresist
oxide or metal
55

• A plasma is a neutral ionized gas, i.e. it
  contains appreciable numbers of free electrons
  and charged ions. Plasmas for etching are formed
  by applying a radio-frequency electric field to a
  gas held at low pressure in a vacuum chamber.
  The applied field will first produce some free
  electrons by photoionization or field emission.
  The electrons are accelerated and undergo a
  series of collisions, resulting in several
  possible reactions
• Dissociative attachment
  eAB?A-Be
• Dissociation
  eAB?eAB
• Ionization eA?A2e
• URL

56

• Because the energy of plasma electrons is much
  higher than a chemical bond energy, molecules in
  a plasma are essentially randomized, breaking
  down into all conceivable fragments. For example,
  a plasma of CH4 can include fragments as CH3,
  CH2, CH, H and C.

• Ions and molecular fragments are highly
  reactive, and can undergo a variety of reactions.
  They are removed from the plasma by
  recombination with electrons, or by reaction with
  chamber walls forming by-products. Any
  microelectronic substrates present in the plasma
  will also react with the energetic species. If
  the reaction products are volatile under the
  plasma conditions, they will evaporate resulting
  in a removal of substrate material. This is the
  nature of plasma etching.

57

• Plasma etching is anisotropic, meaning that the
  downward etch rate is much larger than the
  lateral etch rate. Anisotropic etching is caused
  by the physics, rather than the chemistry of the
  plasma.
• The interior of the plasma is a conductor and is
  thus at an uniform potential. However, the
  plasma is separated from the wall and substrates
  by a sheath where an electric field exists. The
  reason is because both electrons and ions tend to
  leave the plasma near the wall or substrate.
  Electrons, being more mobile and smaller, escape
  more easily. This higher rate of impingement of
  electrons onto any surface causes the surface to
  be negatively charged with respect to the plasma,
  thus repelling electrons and attracting positive
  ions that form a space-charged region near the
  surface. The electric field in the sheath is
  perpendicular to any object immersed in the
  plasma. Thus a substrate is bombarded with a
  stream of ions perpendicular to its surface.

58

• Anisotropy is encouraged by ion bombardment in
  several ways. At sufficiently high energies, the
  bombarding ions simply erode the surface they
  strike by the sputtering process. At low
  energies, ion bombardment can promote chemical
  etching by locally heating the substrate and by
  loosening chemical bonds. In many plasma
  systems, where an inert residue tends to form on
  the substrate, ion bombardment can promote
  anisotropy by sputtering the protective residue
  from exposed areas.

photoresist
Ion residue
polySi
59
5.1 Practical plasma etching equipment (a) The
simplest plasma etching reactor is the barrel
reactor, which holds the wafer vertically in an
electrically floating cassette in a quart chamber
held at 0.1-2.0 torr. The r.f. power is
capacitively coupled to the plasma through large
plates held against the chamber wall. Plasma
sheath potentials to the wafer is small, and ion
bombardment plays a small role in the surface
chemistry. They are mainly used as isotropic
resist removers with oxygen as the source gas.
60
Barrel etcher for plasma etching
61
(b) In reactive ion etching equipment, a planar
reactor configuration is used. Substrates are
laid flat between two closely spaced, planar
electrodes. The result is a much lower capacity,
but higher uniformity of etch. The substrate
electrode is connected to the r.f. power supply,
and the other electrode is connected to the
chamber wall and grounded. This will produce a
high potential (20-500V) between the substrate
and plasma at a low operating pressure (5-100
mTorr). The reason is that plasma theory shows
the following relationship between the electrode
area and voltage drop across the sheath
62
S71
Planer etcher for reactive ion etching
63

• 5.2 Plasma reactants
• Both SiF4 and SiCl4 are gases under plasma
  conditions thus either fluorine or chlorine
  plasmas will etch silicon compounds. A common gas
  used is CF4.. The fluorine atoms in the plasma
  then react with silicon compounds as

64

• Usually the etch rates by fluorine atoms is
  higher for Si as compared to silicon nitride or
  silicon dioxide. The ratio of etch rate for the
  film being etched, to the etch rate of the
  underlying material, is called the selectivity. A
  selectivity of 101 is often required because
  process variations require at least 10-20
  over-etch of the upper film.
• Aluminum can only be etched in Cl containing
  plasma, because AlCl3 is volatile, but AlF3 is
  non-volatile. Plasma etching of Al encounters a
  problem due to the presence of aluminum oxide

65

• . The etching rate of aluminum oxide is much
  slower, causing a long and irreproducible
  induction period before the onset of aluminum
  etching. If the oxide thickness varies across the
  substrate, the aluminum etching also becomes
  highly nonuniform. Boron trichloride plasma
  etches Al with very little induction period, due
  to its slow attack of aluminum oxide. But the
  etch rate is relatively slow. Polymers are not
  formed, and the etching is more isotropic.

66
6. Vacuum deposition In a low pressure system,
the ideal gas law applies where n is the
number of moles of gas present. A gas is said
to be at standard temperature and pressure (STP)
at 1 atm and 0?C. At STP, 1 mole of any ideal gas
occupies 22.4 litres. The kinetic theory predicts
that although molecules move at a velocity
constantly changing through collision, there is a
mean free path, which is the average distance
moved by molecules between collisions.
67
where N is the density of molecules per unit
volume, d is the molecular diameter. MFP is
inversely proportional to N, which is
proportional to pressure. MFP is inversely
proportional to N, which is proportional to
pressure. When a gas flows through a system with
dimensions well below MFP, the flow is viscous.
However, when MFP exceeds system dimensions, the
flow become molecular, i.e. molecules travel in
straight lines.
68
6.1 Deposition by evaporation If a material is
melted in vacuum, it will immediately vaporise.
The vapour molecules are emitted in all
directions, traveling in straight lines until
they strike a surface. The simplest form of
evaporation is by direct heating. But impurities
in the crucible can be incorporated into the
material melted. A better way is to melt the
material by electron beam heating. The beam is
generated under the source and directed between
the poles of a magnet to bend the beam 270?C.
However, X-ray is generated due to excited
electrons falling back to core levels, and may
damage MOS devices.

69
An evaporation source is essentially a point
source. This has implications for the uniformity
of the deposited film. A point source deposits
material onto a surface at a rate r (in thickness
per time) with where revap is the
evaporation rate (mass per time), ? is the solid
angle over which the source emits, ? is the
material density, d is the source-substrate
distance, ? is the angle between the surface
normal and the direction of the source.
70
Microelectronic substrates usually possess
surface topography, and it is important that film
thickness be uniform over steps on the surface.
(This property is called step coverage). For a
point source positioned perpendicular to the
substrate, there will be no deposition at
vertical steps. Step coverage can be improved by
placing the substrates in rotating planetaries
that incline them to the source, or by heating
the substrate to enhance the movement of atoms
after deposition.
Si
71

• 6.2 Deposition by sputtering
• In a plasma large number of positive ions are
  accelerated by the plasma potential and bombard
  the substrate surface. If the bombardment energy
  exceeds roughly 4 times the bond energy of a
  solid, atoms will be knocked loose, providing a
  source of atomized material. Ar gas is often
  used as the plasma source.

• A conductive material can be sputtered by using
  it as the target to form the cathode in D.C.
  sputtering. In the cold dark space close to the
  cathode, there is an electric field accelerating
  the Ar ions to bombard the target. In an r.f.
  discharge, both conductive and insulator
  materials can be sputtered. In order to develop
  a negative d.c. potential at the target, the two
  electrodes (i.e. the target and the substrate
  holder) are made to have unequal areas. The
  target is the small electrode, and the substrate
  holder is connected to the chamber wall as the
  large electrode.

72
Potential in a plasma system
73

• Sputtering yield is defined as the number of
  ejected atoms per bombarding ion. Sputtering
  rate is the number of atoms generated from the
  target per sec per unit area.

• An improvement in sputtering yield is the use
  of magnetron sputtering. In a magnetron, a
  magnetic field is applied at right angles to the
  electric field. This causes the secondary
  electrons ejected from the cathode to spiral
  through the gas and increase the efficiency in
  ionization.

.
Magnetic field into paper
electrode
74

• Sputtering has several advantages over
  evaporation

• i) while evaporation sources are point-like,
  sputtering occurs over a larger target area. This
  improves the step coverage.
• ii) Sputtering can work with many materials, e.g.
  refractory materials that would be difficult to
  be melted.
• iii) Sputtering gives almost the same composition
  in the deposited film as the target, and so is
  excellent for alloys and mixtures.
• iv) The substrate can be pre-cleaned by
  sputtered-etch, where the substrate holder is
  connected to the r.f. supply and becomes the
  cathode.

75
7. Photolithography Photolithography refers to
the process of using an optical image (on a mask
plate) and a photosensitive film (the
photoresist) to produce a pattern on a substrate.
Exposure is mainly to ultra-violet light, but
electron-beam and X-ray can also be used. After
exposure, the substrate is washed with a solvent
that preferentially removes the resist areas of
higher solubility. This step is called
development.
7.1 Resists Optical lithography comprises the
formation of images with visible or ultraviolet
radiation in a photoresist using contact,
proximity or projection printing.
76
Photoresists are of two types. A negative resist
on exposure becomes less soluble in a developer
solution, while a positive resist becomes more
soluble. Commercial negative resist after
exposure swells. The swelling distorts the
pattern features and limits resolution to 2 to 3
times the initial film thickness. In positive
photoresists the unexposed regions do not swell
much in the developer solution, so higher
resolution is possible with possible resists.
Electron exposure of resists occurs through bond
breaking (positive resist), or the formation of
bonds or crosslinks between polymer chains
(negative resist). It has extremely high
resolution but it is of relatively low
resistivity.
77
7.2 Pattern transfer The mask image can be
transferred to the resist by exposure to
ultraviolet light, x-ray , electrons. The
resolution and delineation of the pattern to be
transferred depends on the beam intensity, its
spatial distribution and the beam
width. Contact, proximity, or projection
printing can be used for light beams.

• In contact printing, the mask and resist are in
  direct contact. The major drawback is poor yield,
  because defects in the mask can be caused by
  small particles on the wafer surface, which are
  copied to other wafers. However, very high
  resolution up to 0.2?m is possible.

78

• The defect problem can be avoided by providing a
  gap (10 to 25 ?m) between the mask and resist,
  which is the essence of the proximity printing.
  The resolution is proportional to (?g)1/2, where
  ? is the light wavelength and g is the gap and is
  of the order of a few micrometer.

• Projection printing involves projecting an image
  of the pattern onto the resist surface. Since the
  mask is far away from the resist-coated wafer,
  only a small portion of the mask is imaged at a
  time to achieve high resolution. This small image
  field necessitates scanning or stepping over the
  surface of the wafer and therefore the method is
  also called stepping on wafer printing.
  Resolution can be made close to that of contact
  printing.

79
Projection
Contact
Proximity
Light source
Mask
Photoresist
Gap
Silicon wafer
80
For projection printing, NA is the numerical
aperture, W is the resolution and Z is a limit on
the depth of focus over which image quality is
not degraded. Z imposes severe requirements on
the wafer planarity. Maskless printing can be
achieved by directly driving an electron beam to
write patterns on the resist. The beam is focused
to a spot the same size as or smaller than the
minimum pattern size. With the combination of
beam deflection and shuttering, individual spot
exposures are built up into complete patterns
that are stored on a tape in accordance with the
digitized circuit layout.