Statistical FullChip Leakage Analysis Considering Junction Tunneling Leakage

1
Statistical Full-Chip Leakage Analysis
Considering Junction Tunneling Leakage

• Tao Li Zhiping Yu
• Institute of MicroelectronicsTsinghua University

2
Outline

• Motivation
• Junction Tunneling Leakage Circuit Level
  Analysis
• Simple inverter
• Multi-input gate
• Statistical Full-Chip Leakage Analysis Technique
• Modeling of process-induced parameter variations
• PCA ICA
• Sum of leakage components
• Experimental Results
• Summary

3
Leakage and Process Variations

• Leakage power becomes a major component ofthe
  total power.
• Process variation has a significant impact on
  leakage.

Feature Size Scale Down
4
Major Leakage components

• Subthreshold leakage
• Gate oxide leakage
• Junction tunneling leakage

Gate Leakage Igate
Subthreshold Leakage Isub
Gate
Source
Drain
n
n
Bulk
Junction tunneling leakage
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Overview of Related Works

• Previous works on statistical full-chip leakage
  computation
• Computation of PDF of full-chip leakage
• Approximate process variations asGaussian
  distributions
• Finding full-chip leakage by summing
  upindependent lognormals
• R. Rao ISLPED03,H. Chang ICCAD 03,H. Chang
  DAC05, X. Li DAC06, et al.
• Most of the previous works ignored
• Effect of Non-Gaussian parameters
• Junction tunneling leakage

6
Outline

• Motivation
• Junction tunneling leakage Circuit level
  analysis
• Simple inverter
• Multi input gate
• Statistical Full-chip leakage analysis technique
• Modeling of process-induced parameter variations
• PCA ICA
• Sum of leakage components
• Experimental Results
• Summary

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Simple Inverter

• When input 0V
• NMOS maximum
• Can be independently calculated and added for
  total leakage
• PMOS gate oxide leakage small and ignored
• When input
• NMOS gate oxide leakage
• PMOS subthreshold leakage and junction tunneling
  leakage

0
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Multi input gate general approach

• If all inputs have a high state
• Analysis is similar to the that of the inverter
• At least one input is low
• Combination of , ,and
• Approach distinguish 6 different scenarios

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Computation of Total Chip Leakage

• Total leakage current of a chip

probability of input vector state i of the jth
gate
can be either the leakage for a fixed input
vector or the average leakage current

• Input pattern independent approach
• Direct computation 2k input vector states for a
  k-input gate
• Applying dominant states of
• Leakage of stack at state i is not always
  independent
• Interactions of Isub, Igate and Ijunc need to be
  considered
• Analyzing leakage current of stack by input state

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Dominant States of Leakage Current

• Interaction between Isub and Igate

NMOS-Transistor Stack
D. Lee et. al. at DAC03

• Case (a) (c) dominate states of Igate

C. Oh et. al. at DAC99 D. Lee et. al. at DAC03

• Case (a) (b) dominate states of Isub

• Dominant states of junction tunneling leakage
  Ijunc
• States with the on transistors connected to the
  output node(stack effect )
• Only k dominant states for a k-input gate

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Results Leakage estimation for 4-NAND

• The error of the proposed analysis method over
  SPICE

• Average 1.5 over all input states
• Maximum error 4.5 _at_1110

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Outline

• Motivation
• Junction tunneling leakage Circuit level
  analysis
• Simple inverter
• Multi input gate
• Statistical Full-chip leakage analysis technique
• Modeling of process-induced parameter variations
• PCA ICA
• Sum of leakage components
• Experimental Results
• Summary

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Proposed Analysis Method Highlights
Non-Gaussian and Gaussian variables transformed
to independent basis with PCA/ICA
Incorporates both Gaussian and non-Gaussian
parameters
Inputs are moments of varying process parameters
Easier to obtain moments from process data files
Three kinds of leakage components are considered
Fast algorithm for the sum up of leakage
components
Moments matching-based PDF/CDF extraction
Uses closed form PDF/CDF expressions
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Outline

• Motivation
• Junction tunneling leakage Circuit level
  analysis
• Simple inverter
• Multi input gate
• Statistical Full-chip leakage analysis technique
• Modeling of process-induced parameter variations
• PCA ICA
• Sum of leakage components
• Experimental Results
• Summary

15
Experimental Results

• Comparison of our results with Monte Carlo
  simulations
• Comparison with Gaussian modeling of parameters

16
Outline

• Motivation
• Junction tunneling leakage Circuit level
  analysis
• Simple inverter
• Multi input gate
• Statistical Full-chip leakage analysis technique
• Modeling of process-induced parameter variations
• PCA ICA
• Sum of leakage components
• Experimental Results
• Summary

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Summary

• A fast approach to compute total leakage current
• Considering , ,and
• Average error 1.5
• Both Gaussian and Non-Gaussian parameters are
  considered
• PCA and ICA are employed as preprocessing steps
• Sum the leakage to get a final result
• Algorithm has a complexity of

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• Thanks!