SNS Diagnostic Review BCM System Final Design Review

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SNS Diagnostic ReviewBCM SystemFinal Design
Review

• Martin Kesselman
• 3-13-02

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Outline

• General Overview
• Key Issues
• Approach
• Details
• MEBT, Linac, HEBT, Ring, RTBT
• Testing
• Calibration
• Acceptance Testing Strategy
• Summary

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Schedule
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SNS DESIGN PARAMETERS

• Energy..1 GeV
• Intensity... 1.5 x 1014 protons
• Repetition Rate.....60 Hz
• Number of Bunches..... 1
• Injection duration. 1.0 msec
• Revolution Period.. 945 nsec
• Bunch Length.... 645 nsec
• Number of turns. 1060

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BCM Requirements

• From SNS Diagnostics AP Requirements (03/01)
• MEBT to HEBT 0.3 - 1000 us,
• 15 to 52mA
• Accuracy lt 1 of FSR
• Resolution 0.1 of FSR
• Detail within mini-pulse- available on demand
• Ring to RTBT 5e10 to 2e14 Protons
• 0.015A to 100A
• Accuracy lt 1 of FSR
• Resolution 0.1 of FSR (relaxed to 0.5 for gain
  steps compromise)
• Turn-by-turn data- available on demand

Interpretation of requirements
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Status and Goals

• Prototype driven by MEBT schedule
• MEBT transformers are installed
• HEBT, Ring RTBT transformers awaiting delivery
• MEBT electronics are straight forward
• Prototype shipped to LBNL (Feb 2002)
• Second version of circuit board artwork under
  review
• Goals
• Hardware in Spring

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Beam Current Monitor Distribution
not finalized
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Key Issues

• Measurement of chopper characteristics vs. Ring
  turn by turn current.
• Goal of a single design to minimize design cost,
  and provide interchangeability
• Large dynamic range in Ring and RTBT
• DC restoration and droop compensation
• Integration accuracy vs. sampling rate
• Noise, Response characteristics, filtering and
  digitizing aliasing
• Testing
• Calibration

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SNS Ring Beam Current Readout
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Droop in Current Transformer Signals
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Approach

• Select transformer to accommodate the need for
  examining the chopper edge.
• Provision for fast mini and slower macro
  pulse digitization will be accomplished with
  different digitizers.
• Compensate for droop digitally to permit a single
  transformer design throughout the SNS to simplify
  over-all design by building identical electronics
  for all locations.

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Signal Conditioning

• Basic approach is to digitize as-soon-as
  practical and do all signal conditioning
  digitally.
• Provision for fast mini and slower macro
  pulse digitization will be accomplished with
  different digitizers.

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Base-line Restoration Approach

• An algorithm that will compensate for the droop
  can be used.
• Using a no signal average to determine DC
  offset and subtract from data provides Base-line
  Restore .
• Droop Compensation achieved by an IIR filter
  algorithm.

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Droop Compensation
Transformer Transfer function T(s)Ks/(s1/?L)(
s1/?H)
Compensation
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Adjustment of Droop Compensation
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Sensitivity to Transformer Droop Time Constant
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Sensitivity to Errors in Sampling Time
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Screen Dump BCM0.4 (1-17-02)
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General BCM Signal Processing
FCT
14 Bit 60MSa/S
INPUT SIGNAL CONDITIONING ADJ. GAIN
CURRENT
BEAM
HISTORY
OUTPUT DATA FORMATTER
CURRENT DATA
Frev
INTEGRATOR accumulator
MINI-BUNCH CHARGE
INTEGRATOR accumulator HEBT ONLY
Frev /N
MACRO-BUNCH CHARGE (HEBT)
DIGITAL PROCESSING
8 Bit 1GSa/S
INPUT SIGNAL CONDITIONING ADJ. GAIN
MINI-BUNCH DATA ACQ. SYSTEM
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MEBT/Linac/HEBT Analog Front End Digitizer
Block Diagram
150 FCT 15mA to 60 mA
RESISTIVE MATCHING 100 50 OHMS
WIDE-BAND OUTPUT
BESSEL FILTER 5 Pole 7MHz LP
50 Ohm Resistor -6dB
AD600 0dB to 40dB
35dB
0.211 V for 15mA 0.846 V for 60mA
7.5mV to 30 mV
29dB Gain
SINGLE PRE-SET GAIN
8 Bits
FRONT END
GAIN
REG.
1.05MHz rf
DIGITAL INTERFACE
AD6644 14 Bit /- 1.1V
AD8138 Diff. Out
ANTI-ALIAS FILTER
14 Bits
DATA
0.21 V for 15mA 0.85 V for 60mA
40MHz or 60MHz Clock (continuous)
DIGITIZER
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Using FCT for HEBT Averaging BCM
Estimated Total Noise at ADC for a 7MHz BW FCT
with 150 Turns Ratio, AD600 with Vn1.5nV/rtHz
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Bandwidth Considerations-1

• The system bandwidth hasbeen set to 7MHz as a
  compromise in noise, response characteristics,rec
  overy to lt 0.1 during the "gap" time, and
  anti-aliasing issues.

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Bandwidth Considerations-2

• Chopper Edges (10nS rise time)
• Requires gt100MHz
• MiniMacro-pulse Ring general shape analysis
  (50nS rise time)
• Requires gt7MHz
• Select Gaussian response for transient
  characteristic to minimize overshoot
• Settling Time
• Response to settle within the 300ns gap time (7
  MHz filter settles in lt 150ns)
• Resolution
• Requires an analysis of noise (7MHz estimate is
  about 0.1 of 1/2 scale)

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Bandwidth Considerations-3

• Anti-aliasing
• A 5 Pole 7MHz Gaussian filter provides about 43dB
  attenuation at 34MHz.
• Adding an additional 5 Pole 17MHz 0.01dB
  Chebyshev filter will provide an additional 37dB
  attenuation at 34MHz.
• Total attenuation at 34MHz is 77dB, an additional
  -6dB (two stages) for band limited amplifiers
  yields 83dB attenuation (gt13 bits, 1.2LSB).
• The variable gain amplifier has a 35MHz
  bandwidth, adding a band-limited summer stage, or
  filter driver stage provides the necessary
  additional attenuation with minor pulse overshoot
  (lt5), and bandwidth shrinkage.
• Digitizer aliasing held to better than -80dB at
  Nyquist (0.007).

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Sampling Frequency Considerations

• The earlier discussion of anti-aliasing assumed a
  near 70MHz sampling rate
• Calculation of charge involves an integration of
  the current signal. An analysis of integration
  errors shows one requires a minimum of 25MHz
  sampling rate to achieve 0.1 accuracy.
• It is desirable to be synchronized with the
  revolution frequency so that samples are nicely
  related to mini-pulses, simplifying software
  algorithms.
• Reference available is 16Frev (16.9MHz)
• Therefore, convenient multiples are 33.8MHz or
  67.7MHz
• AD6645 is available in 80MSPS or 105MSPS 14 Bit
  ADC versions (pin compatible with AD6644)

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Integration Accuracy for Charge Calculation
16MHz
0.2
0.1
64MHz
32MHz
0.04
Courtesy of Alexander Aleksandrov
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Analog-Digital Partitioning

• Presently, prototyping of other diagnostics is
  taking place at both LBNL and LANL.
• To use these efforts to advantage, the present
  prototyping configuration will be partitioned to
  permit the use of a digital interface under
  development at LANL.
• Can employ separate boards, or grouping Analog
  front end with digitizer.

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BCM BPM Partitioning Options
Separate Boards?
SETTING INFO
SETTING INFO
Gain, Ref., etc.
Gain, Ref., etc.
TIMING REFERENCES 60MHz Sampling Clock RING Ref.,
etc.
DIGITAL INTERFACE Averaging, Circular Buffer,
Gain Memory, Gain Correction, Baseline
Restore, Integration, Time-stamp
ANALOG FRONT END and BAND-LIMITING
DIGITIZER
SENSOR
DIFFERENTIAL INPUT
DIFFERENTIAL INPUT
STATUS
STATUS
Digitizer with Interface
Digitizer with Analog Front End
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Ring Large Dynamic Range Considerations

• Requires switched gains (loss of one turn data
  during switching is acceptable)
• Signals will be large (50 Volts peak for 100
  Amps)
• amplifiers require protection
• solid state switches must handle the voltage

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Ring BCM Protected Pre-Amp Concept
RESISTIVE MATCHING R 50 OHMS
WIDE-BAND OUTPUT
150 FCT 15mA to 100 A
GAIN SET
Zi50
GAIN
8 Bits
REG.
1.05MHz rf
7.5mV to 50 V
PROTECTED PRE-AMPS WITH DIFFERENT
SELECTED ATTENUATION AND TWO STATE OUTPUT
Amp select
FILTERs 5 Pole 7MHz LP 5 Pole 17MHz
TO ADC
50 Ohm Resistor -6dB
0.211 V for 15mA 0.846 V for 60mA
BUFFER AMP
BUFFERED OUTPUT
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Protected Pre-amp
For the attenuator ?Zi/ Zi2(?ZL/
ZL)/2N(N-1) (?ZL/ ZL) N power
ratioPi/Po ZL161Zi Zi V/I
V/(V-Vd)/1.96K 1.96K(1 Vd/V) For
Vd/V1/500.02 ?ZL149.000648-148.7788 .2218
and (?ZL/ ZL)0.001491 For the 3dB pad N2 and
?Zi/ Zi .074
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Criteria for Ring Gain Selection

• Achieve linearity to 100 Amps
• Achieve 0.1 resolution, assume ADC noise is
  -74dBV (200uV)
• Let 50 Amps correspond to 25 Volts at transformer
  output when terminated in 50 Ohms, and 0.5 volt
  (1/2 scale) at ADC.
• Minimum signal to ADC should be about 0.2 volts
  for 0.1 resolution
• Signal ratio required before a gain change is
  2.5(based on 50mA signal). Requires 8 gain
  changes
• Relaxing resolution to 0.5 reduces minimum
  signal to 40mV and requires only 3 gain changes

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Gain selection for 0.1 Resolution

• Number of gain changes required to handle 10001
  ratio is
• n3/log(2.5)7.5
• Can use 7 to 8 gain changes with about 2.51
  ratios

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GAIN CHANGING FOR 0.5 RESOLUTION
12 dB G4 Protected
15050
24.5 dB 8.1dB
MONITOR
G67 G7.2
0V-35V
150150 -3dB
T1-T3
0V-50V 0-100A
29 dB G28.2
15050 -28.2dB
G1.09
0-1.95V
G0.039
T4-T26
SWITCH AMP
100100 -6.25dB
8.35 dB G2.615
G0.102
G0.019
T27-T276
0 dB G1
G0.019
0-0.95V
T277-T1060
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Gain Control - Using Switched Amplifiers
OPA680 AMPLIFIERS
SUMMER
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ADC Driver Section
34MHz BAND-LIMITED SUMMER
34MHz BAND-LIMITED BUFFER
PULSE SHAPER
ANTI-ALIAS FILTER
7Mz 5 POLE GAUSSIAN FILTER
17 MHz 0.01dB 5 POLE CHEBYSHEV
AD8138 DRIVER
14 BIT DATA
AD6645 ADC 80 MHz 14 BIT
68MHz Clock locked to Rev Freq.
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Using FCT for Ring Averaging BCM
Estimated Total Noise at ADC for a 7MHz BW FCT
with 150 Turns Ratio, ADC 246uV, AD600 418uV,
OPA620 38uV Relaxed resolution to 0.5 permits 4
gains or 3 gain changes
Protected Variable Gain Variable gain
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Using FCT for RTBT Averaging BCM
Estimated Total Input Noise for a 7MHz BW FCT
with 150 Turns Ratio
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Testing

• To test transformers two test fixtures have been
  built.
• Fixtures were prepared from 3-1/8 8 inch 50 Ohm
  coax, with a break placed in the shield. A
  shroud carries the wall currents around the
  transformer.
• This accommodates changing transformers quickly.

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Prototype Board Under Test at BNL 12-21-01
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BCM Testing Fixture
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CALIBRATION

• Each FCT has a built in 10 turn calibration
  coil. Allows for calibration (a sample
  transformer passes a 700ns pulse with 50ns rise
  time).
• Bergoz has designed the 10 turn calibration
  coil for best coupling, and the ability to
  simulate large currents.

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Calibrator Requirements

• Remotely controlled
• Provide a 50 Ohm termination for the calibration
  winding
• Current output DAC with appropriate termination
• Provide a verifiable current pulse
• Use a current output DAC to a 50 Ohm load
• Measure open circuit voltage and short circuit
  current off-line to calibrate the calibrator.
• Use Thevenin Equivalent to calculate current
  applied.
• Monitor output current as a back-up

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Calibrator
Ground Isolated Current output DAC
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Acceptance Test Strategy

• Boards/PCs to be tested at BNL prior to shipment,
  and after delivery to ORNL
• Use internal calibrator to stimulate the
  electronics and compare engineering parameters
  with measurements made earlier.
• Some things to check
• ability to perform DC restoration and droop
  compensation (droop lt 0.1/ms).
• determine resolution of particle computation, and
  current measurement (lt0.1 FS).
• confirm accuracy of current measurement better
  than 1 FS.
• confirm system response shape and bandwidth (7MHz
  /- 10).

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Conclusions

• Protected gain switched amplifier selection
• Focusing on digitizing as-soon-as practical
• Use two different digitizers for detailed
  mini-pulse information, and macro-pulse detail
• Perform base-line restoration, droop compensation
  other analysis digitally
• Incorporate efforts of partner labs to minimize
  the design effort.
• Number of gains for Ring is a function of
  resolution required.

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Testing Berkeley Prototype at BNL - 12/21/01