Lets Look At Timing Analysis

1
Lets Look At Timing Analysis

• Design
• Break down into tasks.
• Estimate/analyze timing.
• Programming
• Program each task.
• Estimate/analyze timing.
• Determine feasibility of schedule.
• Validation and Testing (estimate/analyze timing)
• Component level.
• System level.

2
Timing Analysis

• You write
• for (i0iltni)
• for (j0jltmj)
• if (Im(i,j)gtthreshold)
• counti
• if (counti gt counti-1)
• break
• What is the WCET?
• This is a very important and difficult question.

3
WCET

• definition
• upper and lower bounds
• safe and tight

4
Methods and Goals

• Static Analysis
• Measurement-Based
• Goals
• affordable
• sufficiently precise
• tractable
• easy

5
Influences

• input
• logic
• hardware

6
Timing and Architecture

• RISC vs CISC
• pipelining
• caches
• processor speed
• co-processors
• dual processors
• machine instructions
• memory characteristics

7
A Simple Architecture
for (i0iltni) for (j0jltmj) if
(Im(i,j)gtthreshold) counti if (counti
gt counti-1) break
8
Fetch-Execute Cycle
for (i0iltni) for (j0jltmj) if
(Im(i,j)gtthreshold) counti if (counti
gt counti-1) break
9
CISC vs RISC

• RISC
• Reduced Instruction Set Computer
• Single clock cycle per instruction
• Complexity is in compiler Instruction executed by
  hardware
• Highly pipelined

• CISC
• Complex Instruction Set Computer
• Multiple clock cycles per instruction
• Complexity in microprogram and HW
• Harder to pipeline
• Several Cycles per macroinstruction (machine
  code)

10
Pipelining anticipating the next instruction
11
Pipelining

• Out-of-order execution (speculation)
• Hazards
• Data
• Branching
• Structural

12
Cache
Locality of Reference distance in memory
between consecutive code or data
for (i0iltni) for (j0jltmj) if
(Im(i,j)gtthreshold) counti if (counti
gt counti-1) break
block 2 block 3
13
Cache

• Characteristics
• capacity
• line size (block size)
• associativity
• Types

14
Cache

• Replacement Strategy
• Write Policy
• Cache hit or miss
• Cache hit ratio average of time needed item
  is in cache

15
Timing and Architecture

• RISC vs CISC
• pipelining
• caches
• processor speed
• co-processors
• dual processors
• machine instructions
• memory characteristics

16
Influences

• input
• logic
• hardware
• compiler optimization
• interrupts

for (i0iltni) for (j0jltmj) if
(Im(i,j)gtthreshold) counti if (counti
gt counti-1) break
17
Problems in WCET Analysis

• Path Problem
• infeasible paths
• halting problem
• longest path

18
Problems in WCET Analysis

• State Problem
• intractability
• local vs global analysis
• divide-and-conquer
• context (TRPS timing-relevant processor state)
• control-flow interference
• data memory interference
• timing anomolies

19
Problems in WCET Analysis

• State Problem
• timing anomolies

20
Architecture of Timing-analysis Tool
WCET prediction by static program analysis. A
white paper from http//www.absint.de/wcet.htm
21
Methods and Goals

• Validation and Testing (estimate/analyze timing)
• Component level.
• System level.
• Static Analysis
• Measurement-Based
• Goals
• affordable
• sufficiently precise
• tractable
• easy