MinimumEnergy LDPC Decoder for RealTime Mobile Application '

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Minimum-Energy LDPC Decoder for Real-TimeMobile
Application.

• Weihuang Wang, Gwan Choi, Design Automation
  Test in Europe Conference Exhibition, 2007.
  date07

Presented by Cheng-Kang Li Apr 17, 2008
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Outline

• Introduction
• LDPC Codes
• Circuit power estimation and reduction
• Proposed low-power real-time decoding
• Result
• Conclusion

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Introduction

• Real time content delivery for wireless portable
  devices.
• LDPC codes.
• 1.Low-Density Parity-check Codes.
• 2.Near Shannon limit performance and high
  throughput.
• 3.Use message-passing algorithms exchange
  information between the bit nodes and check nodes
  in an iterative fashion.
• Dynamic voltage and frequency scaling (DVFS)
  techniques.

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LDPC CODES

• LDPC codes are defined by a sparse parity check
  matrix H Hmn that consists mostly of 0s.
• H matrix of (n, dc, dv) regular LDPC code
• n, k ,m , code rate k/n 1 - dv/dc.
• Irregular and regular LDPC codes.

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LDPC CODES

• LDPC codes is based on the iterative
• message-passing algorithm.
• Check-node processing and variable-node
  processing.
• Reduce the decoding complexity in implementation.

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LDPC CODES

• LDPC code represent by a bipartite graph
  consisting of two types of nodesvariable
• nodes and check codes.

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Circuit power estimation and reduction

• There are three major sources of power
  dissipation in CMOS circuit

• Switching power is the main source of power
  dissipation in the circuit.

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Policy
Circuit power estimation and reduction

• Key the decoding process is finished before the
  maximum number of decoding iterations.
• Energy saving can be achieved by lowering the
  decoder performance level.
• Performance adjustment is feasible because
  severity of noise corruption of channel data can
  be estimated in advance from the decoding process
  itself.

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Policy

• The maximum number of decoding iteration for each
  frame is dynamically adjusted.
• The maximum number of decoding iteration is set
  to be close to optimum in terms of energy and
  coding performance.
• Based on randomly constructed (3, 6) rate 1/2
  code with block length of 2048 over a block
  fading channel.

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Policy
Probability density function of number of check
error.
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Policy

• The more checks in error, the more decoding
  effort is needed.

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Policy

• The average number of decoding iterations for
  multiple frames is highly correlated with SNR,
  and almost all frames are decoded after 1.5 times
  of the average decoding iterations.

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Policy

• Based on the information of average decoding
  iterations of past few frames and number of
  checks in error for incoming frame, we can
  estimate an upper bound for the decoding
  iteration with high confidence level.

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Policy
The policy is described in the following codes
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Design
Circuit power estimation and reduction

• The above policy can be implemented with low
  hardware complexity.
• The best solution for managing power is
  maintaining the highest performance as long as
  possible and then turning the circuit into sleep
  mode.
• In the case of LDPC decoder is not feasible,
  because of the real time constraints.
• Operating at low clock frequency, the voltage
  supply can be lowered correspondingly.

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Design
Block diagram of controller

• cHT of the incoming data frame Fi, is used to
  predict the number of decoding cycles, hence the
  decoding frequency can be determined.

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Design
Buck converter
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Result

• Extra 5 timing margin has been added to the
  critical path replica in the controller to
  accommodate variations.

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Result

• Assuming a 500MHz system clock, it can be divided
  into 167MHz, 125MHz, 100MHz and 84MHz for
  decoder.

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Result
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Result
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Result

• 30 power is saved without bit-error degradation
  and minimum frame-error rate loss.

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Result

• The increased saving is due to the fact that the
  small probability of a bit being corrupted by
  channel noise when SNR is high.

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Conclusion

• Larger number of decoding iterations is used for
  critical data frames to maintain high coding
  performance, smaller number of iterations, lower
  frequency, and hence lower power supply are used
  for data frames less severely damaged by noise in
  order to save power.
• Up to 30 power saving in decoding process is
  achieved without performance degradation.

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Thank You