Robust Gate Sizing by Geometric Programming

1
Robust Gate Sizing by Geometric Programming

• Jaskirat Singh, Vidyasagar Nookala, Tom Luo,
  Sachin Sapatnekar
• Department of Electrical and Computer Engineering
• University of Minnesota

2
Outline

• Introduction
• Motivation
• Robust gate sizing
• Impact of variations on the conventional gate
  sizing solution
• Uncertainty ellipsoid
• Robust GP formulation
• Incorporating spatial correlations
• Experimental results
• Summary

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Introduction

• Impact of increasing variability in design

Theres many a slip between the cup and the lip
!!
Process uncertainties
Environment variations
Tool inaccuracies
L0
What you draw is NOT what you get!!

• Timing yield of the circuit affected

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Gate Sizing Problem
Minimize Area (Power) Subject to Delay
Dspec Xmin X Xmax
Gate size

• Previous work
• Fishburn and Dunlop, ICCAD 85
• Sapatnekar et. al, TCAD 93
• Chen et. al, TCAD99

A number of dies have to die!!

• Do not account for variations
• Circuit optimized for a specified delay

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Robust Gate Sizing Solutions
delay specs new
delay specs original

• Traditional worst-casing techniques
• Set tighter specs than required
• May lead to large overheads

of chips

• Corner based designs
• Design for extreme values of the parameter
  variations
• Ignores correlations betweenrandom variables
• Curse of dimensionality

delay
slack

• Statistical Designs

pmin p pmax
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Proposed Robust Gate Sizing Method
A novel worst-casing methodology
Incorporates spatial correlations
Only covariances of random parameters required
No assumptions about parameter distributions
Robust formulation is a Geometric Program
Efficient and accurate solution
7
Outline

• Introduction
• Motivation
• Robust gate sizing
• Impact of variations on the conventional gate
  sizing solution
• Uncertainty ellipsoid
• Robust GP formulation
• Incorporating spatial correlations
• Experimental results
• Summary

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Conventional Gate Sizing Solution
Min Area (W, L) Subject to Delay (W, L)
Dspec Wmin W Wmax
LLmin
Area, Delay are posynomials in (W, L)
Posynomial delay models, e.g., Elmore delay -
Replace each gate by RC elements
Delay constraints at the output of each gate
Solve the GP by convex optimization tools
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Impact of Variations on Gate Sizing

• Parametric variations as random variable (W, L)
  vary as (W0dW, L0dL)

Effect on delay constraints
and constraint function
Define
Using first order Taylor series
Nominal term
Variation term
Delay constraints Nominal term Variation term
ti
Violations if Variation term gt Slack
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Outline

• Introduction
• Motivation
• Robust gate sizing
• Impact of variations on the conventional gate
  sizing solution
• Uncertainty ellipsoid
• Robust GP formulation
• Incorporating spatial correlations
• Experimental results
• Summary

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Uncertainty Ellipsoid Model
x
An ellipsoid set
z
y
Substituting
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Uncertainty Ellipsoid Model

• Ellipsoid uncertainty model
• Bounded model for random variations

random variations
nominal design
covariance matrix

• More realistic than an
• n-dimensional box

• Aids in incorporating spatial correlations

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Outline

• Introduction
• Motivation
• Robust gate sizing
• Impact of variations on the conventional gate
  sizing solution
• Uncertainty ellipsoid
• Robust GP formulation
• Incorporating spatial correlations
• Experimental results
• Summary

14

Robust Gate Sizing Procedure

• Generate posynomial delay constraints by STA
• Use Elmore delay for simplicity
• Any generalized posynomial constraints may be
  used
• Kasamsetty, Ketkar and Sapatnekar, TCAD98.

Using first order Taylor series for variations
around nominal values
Nominal term
Variation term
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Robust Gate Sizing Procedure

• Nominal term Variation term ti

• Use the ellipsoid uncertainty model

• For robustness
• Nominal term Max dX?U (Variation term) ti

This is still a posynomial!!
An example follows
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Example
Convert each original posynomial constraint to a
set of posynomial robust constraints
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Example
First order Taylor series approximation
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Example
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Example
Use uncertainty ellipsoid model
Using Cauchy Schwartz inequality
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Example
(W1 , L1 )
(W2 , L2 )
2
1
Define robust variables r1, r2
A set of posynomial robust constraints
P covariance matrix Pij 0
is a posynomial
is a posynomial with -ve coefficients
are posynomials
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GP Method

• Convert each original constraint to a set of
  robust constraints

• Cost of at most two additional variables per
  constraint

• Increase in problem size
• Variables O(V)O(E)
• Constraints O(E)

• Robust formulations is still a GP

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Incorporating Spatial Correlations

• Use the spatial correlation model of
• Chang and Sapatnekar, ICCAD03

• P covariance matrix

• Uncertainty ellipsoid characterized by P

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The Complete Procedure
Generate Elmore delay based constraints by STA
Taylor series expansion of constraint functions
Model variations as an uncertainty ellipsoid
Generate robust constraints
Solve the GP
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Experimental Setup

• ISCAS85 benchmark circuits optimized
• 20 L, 25W 3s variations assumed
• Tspec set as 15 slack point
• MOSEK solver for the GP
• Monte Carlo simulations for timing yield
  determination
• 5000 samples drawn assuming multivariate normal
  N(X0 ,P)
• Non-robust designs compared with robust designs

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Results
Monte Carlo simulations for timing yield
determination
A comparison of robust and non-robust sizing
solutions
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Results

• Area-robustness tradeoff
• Size of the uncertainty ellipsoid determines the
  amount of guard-banding desired

s3 2.25 s
s1 1.05 s
s2 1.50 s
W
W
W
L
L
L
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Results
Area-robustness tradeoff and comparison with
conventional worst-case design
Robust design has fewer violations than
worst-case design with the same area
s1 21, s2 14, s3 4
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Summary

• Propose a novel uncertainty aware gate sizing
  scheme
• Use an uncertainty ellipsoid to model random
  variations
• Incorporate spatial correlations
• Robust formulation relaxed to a GP
• Timing yield of robust circuits improves 3-4
  times
• Better than the conventional worst-casing method

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THANKS!!
30

• The next 2 slides are backup slides

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Conventional Gate Sizing Solution

• Formulated as a Geometric Program (GP)

• A brief review of GP
• Definitions
• Monomial
• 0.78 x -1.23 y 2.54
• 1.2u 2 v -1
• Posynomial is a sum of monomials
• - e.g., Posy(u,v,x,y,z) 0.78 x -1.23 y 2.54
  1.2u 2 v -1

GP Min fo(x) Subject to fi(x) 1 i
1,,n gj(x) 1 j 1,,k
Posynomial
Posynomials
Monomials
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Robust Gate Sizing Solutions

• Statistical Designs
• Agarwal, Chopra and Blaauw, DATE05
• Choi and Roy, DAC 04
• Raj and Wang, DAC 04
• Mani and Orshansky, ICCD04
• Jacobs and Berkelaar, DATE 00

• Key ideas in previous works
• Delay constraints generated by SSTArather than
  STA
• Assumptions about delay distributions
• Do not consider spatial correlations
• Solve a general non-linear optimization problem

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Impact of Variations on Gate Sizing

• Delay constraints
• Nominal term Variation term ti

Objective Function
New Feasibility Region
Feasibility Region
Nominal Design
Robust Design

• Violations if
• Variation term gt Slack