Low Power Design of Electronic Circuits

1
A 32-bit ALU with Sleep Mode for Leakage Power
Reduction
Manish Kulkarni Department of Electrical and
Computer Engineering Auburn University, Auburn,
AL 36849 mmk0002_at_auburn.edu
2
Objectives

• Modify existing ALU circuit to incorporate
  Sleep mode in order to reduce leakage power
• Study the effect of Sleep transistor network
  on the ALU circuit in Active and in Sleep mode
• Design a Sleep transistor network for maximum
  Leakage Power savings for a given delay overhead
• Find a set of vectors which causes minimum
  leakage power in ALU during the sleep mode

3
Power Gating
(c) Both Header Footer Switches for
power gating

• Header(PMOS)
• Switches for power gating

(b) Footer(NMOS) Switches for power
gating
David Chinnery, Kurt Keutzer, "Closing the Power
Gap Between ASIC Custom, Tools and Techniques
for Low-Power Design", chapter 10, authored by
Jerry Frenkil, co-author Srini Venkatraman,
Springer 2007.
4
Circuit Diagram
VDD
Data 1
32 - bit ALU (Low Vt)
32
Data 2
Data Out
32
32
Add / Sub
GND_V
Sleep
5
Design of Sleep Transistor

• It is a tradeoff between Saving in Leakage
  power and Speed
• This method tries to Minimize Leakage power
  during sleep mode for a given delay penalty

Delay of a Gate without Sleep transistor is given
by
Delay of a Gate with Sleep transistor is given by
Where, a is Velocity Saturation Index (1lt a lt
2) a 1.8 for 45nm
Anis, M., Shawki, A., Mahmoud ,M., Elmasry, M.,
Dynamic And Leakage Power Reduction In MTCMOS
Circuits Using An Automated Efficient Gate
Clustering Technique, Proc. of the 39th
conference on Design Automation, June 2002, pp.
480-485
6
Design of Sleep Transistor (Cont..)
Allowing 5 overhead on delay
The current flowing through Sleep transistor is
expressed as
This is obtained by simulating the ALU circuit
and finding the Maximum current through GND
Where, µn Electron mobility 150 cm2/V.s at
90oC Cox 19.7 X 10-7 F/m for 45nm VtL 0.466 V
, VtH 0.6226 V and VDD 1.1 V for 45nm The
Sleep transistor size is then obtained as
4774.4 4800
7
Circuit Diagram
VDD
Data 1
32 - bit ALU (Low Vt)
32
Data 2
Data Out
32
32
Add / Sub
GND_V
T1
T2
T3
T79
T80
Sleep Transistor Network (High Vt)
8
Experiment Setup

• The 32-bit ALU circuit is tested for 200
  random vectors of 65 bit each
• The vectors are applied with to the circuit in
  following modes
• 200 vectors with Sleep 1 i.e. Active Mode
• 200 vectors with Sleep 0 i.e. Sleep Mode
• 200 vectors with Sleep changing from 1? 0 after
  100 vectors to get Sleep time
• 200 vectors with Sleep changing from 0?1 after
  100 vectors to get Wakeup time
• During Sleep mode with 200 vectors a Minimum
  Leakage power consuming vector is identified

Some of Results from this experiment have been
shown in following slides.
9
Active Mode
Average Dynamic Power -1.804 dBmW 660.0
uW Average Leakage Power - 14.683 dBmW 34.01
uW
10
Sleep Mode
Average Dynamic Power -35.197 dBmW 302.204
nW Average Leakage Power - 36.174 dBmW
241.32 nW
11
Sleep Time
Time taken by the Sleep transistor network to
bring circuit to sleep mode after the Sleep
signal is asserted. Sleep time 14nS
12
Wakeup Time
Time taken by the Sleep transistor network to
bring circuit to normal operation (active) mode
after the Sleep signal is de-asserted. Wakeup
time 0.4nS
13
Sleep Mode Power for Complete Vector Set
Min. Leakage Power -38.948 dBmW 0.1274 uW
Observed when Input vectors 0X3FB1F6F7
0X84AA877B are applied.
Minimum Leakage Power Vector _at_ 6.9 uS
14
Circuit Diagram (Modified)
VDD
Data 1
32
0X3FB1F6F7
32 - bit ALU (Low Vt)
Data 2
Data Out
32
0X84AA877B
32
Add / Sub
GND_V
T1
T2
T3
T79
T80
Sleep Transistor Network (High Vt)
15
Active ? Sleep with changing input vectors
16
Active ? Sleep with Min. Power Vector at input
Power Consumption during sleep mode when vectors
are varying at the input
Power Consumption during sleep mode when constant
vector is applied at the input
17
Summary of Results
Normal ( uW) Sleep (nW) Power Saving () Sleep Mode with Min Leakage Input Vector Power Saving ()
Avg. Dynamic Power 660.0 302.204 99.95 0 nW 100
Avg. Leakage Power 34.01 241.32 99.29 127.4 nW 99.61
Peak Power 5040.5 1361.131 99.79 127.4 nW 99.99
Minimum Power 29.2549 127.4 99.56 127.4 nW 99.56
Sleep Time 14 nS
Wakeup Time 0.4 nS
Area Overhead 1456 ? 1536 CMOS devices ( 45.05)
The area overhead can be reduced by reducing
number of sleep transistors through clustering.
18
References

• Michael Keating, David Flynn, Robert Aitken,
  Alan Gibbons, Kaijian Shi, Low Power
  Methodology Manual for System On Chip design
  Springer 2008
• Zhigang Hu, Alper Buyuktosunoglu, Viji
  Srinivasan, Victor Zyuban, Hans Jacobson, Pradip
  Bose, Microarchitectural Techniques for Power
  Gating of Execution Units,proc. Of ISLPED 2004,
  pp. 32-37
• Bushnell, M., Yu, B., A novel dynamic power
  cutoff technique(DPCT) for active leakage
  reduction in Deep Submicron CMOS circuits, Proc.
  Of ISLPED october, 2006, pp. 214-219
• Neil H.E. Weste, David Harris, CMOS VLSI
  Design Third Edition, Boston Pearson, 2005
• David Chinnery, Kurt Keutzer, "Closing the
  Power Gap Between ASIC Custom, Tools and
  Techniques for Low-Power Design", chapter 10,
  authored by Jerry Frenkil, co-author Srini
  Venkatraman, Springer 2007.
• Anis, M., Shawki, A., Mahmoud ,M., Elmasry, M.,
  Dynamic And Leakage Power Reduction In MTCMOS
  Circuits Using An Automated Efficient Gate
  Clustering Technique, Proc. of the 39th
  conference on Design Automation, June 2002, pp.
  480-485