HDR Gate Level Presentation

1
HDR- Gate Level Presentation

• Team M1
• Emeka Ezekwe (M11)
• Chris Thayer (M12)
• Shabnam Aggarwal (M13)
• Charles Fan (M14)

Team M1 Manager Matthew Russo
2
Status

• Complete
• Specification definition
• Block Diagram
• C Implementation
• Verilog
• Schematic
• Incomplete
• Layout
• Testing

3
HDR in the G80 GPU (Change to graphical)

• Our decoder is designed to interface between
  specially encoded textures stored on the GPUs
  memory and one of the GPUs texture caches that
  feed into the shader processor.
• Each ROP on nVidias g80 is capable of processing
  4 pixels per clock cycle. We plan for our
  hardware to decode the texture information for 4
  pixels during each clock cycle.
• This decoder will allow smaller textures to be
  stored in the GPUs memory, which will allow
  graphics cards to provide the same functions with
  less memory.
• Ultimately, this decoder can provide savings in
  cost, power consumption, heat dissipation, and
  size in current graphics cards.

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HDR in the Real World
HDR
http//www.nvidia.com/object/IO_37100.html
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Texture Cache
Register
HDR Decoder
Global Memory
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Design Decisions

• Use mirror adders
• 3 Pipeline stages
• OAI/AOI

7
Block Diagram
8
Reg
Compute 1 pixel
Reg
16
Serialize output
7
Reg
Find G
Compute 1 pixel
Int to FP
Reg
16
Serialize output
7
Reg
4
Compute 1 pixel
Reg
Reg
16
Serialize output
4
Reg
4
Reg
Compute 1 pixel
Reg
16
Serialize output
4
Reg
8
Critical Path
9
Integer Multiplier
7
7
Modified Booth Encoder
7
Partial Products
40
Wallace Tree
14
14
Out
14 bit Addition
10
Partial Product Generation
11
Wallace Tree
12
14-bit Carry Select Adder
13
Floating Point Multiply
14
Integer to Floating Point
7
3
1-drag
1
gtgt1
encoder
11
7
6
7
ltlt1
ltlt
5b11111
I-
5
3
21 Mux
5
5b10001
3
OR
15
Integer to Floating Point
16
Mirror Adder
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Mirror Half Adder?
18
Updated Transistor count
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Problems and Questions

• Optimization
• Stop using inverters in the mirror adders
• Take advantage of inversion property within the
  adders and Wallace tree.