Control Theoretic Approach to Dynamic Voltage Scaling

1
Control Theoretic Approach to Dynamic Voltage
Scaling

• Sandy Klemm
• Advisors Ankush Varma and Dr. Bruce Jacob

I. Introduction
II. Mathematical Theory
III. Problem Solution
The scheduling interval is defined to be the unit
of time after which the operating system performs
voltage scaling and frequency setting tasks.
Utilization is defined to be the ratio of busy
to total processor cycles in a given scheduling
interval. Speed is defined to be the fraction
of the maximum clock frequency at which the CPU
is running. Workload is defined to be the
fraction of maximum computational power (busy
cycles per second) which is being used.
Demand is defined as the utilization
given that speed is equal to 1. Theorem 1
Workload equals demand given that utilization is
less that unity.
Dynamic voltage scaling (DVS) is a technique used
in low power embedded systems to reduce energy
consumption while maintaining minimal degradation
in performance. DVS schemes adaptively adjust
clock frequency and voltage levels in an effort
to minimized energy consumption. For CMOS
devices, power consumption is proportional to the
driving frequency and quadratically related to
the supply voltage i.e., instantaneous power
varies with voltage and frequency according to
the relation
where, in low-power
systems, f is the maximum attainable frequency at
which the device can perform consistently given
the supply voltage, V. Hence if the frequency is
scaled, the voltage is scaled proportionally.
Since energy absorbed from t0 to t1 is given
by it is evident that scaling frequency and
voltage proportionally by a constant C will
result in a total energy reduction of C2.
Current DVS schemes are ad hoc, sacrificing
performance unacceptably under high workloads. It
is proposed in this work that a heuristic
approach be integrated within a feedback
control algorithm to exploit a new metric
namely, workload. This paradigm has been realized
in an algorithm and our assumptions
quantitatively verified under a cycle-accurate
M-CORE simulator.
Current DVS strategies rely on utilization as a
descriptive metric for characterizing current
demand and predicting future computational
requirements. The proposed DVS algorithm utilizes
the unique relationship between actual demand and
workload (theorem 1) by exploiting the frequency
independence of workload. The algorithm is
divided into two distinct task workload
prediction and speed setting. Workload prediction
involves feedback though a discrete PI controller
to adaptively estimate workload and demand. The
predicted workload is given by the following
expression where Wp,Wm, Kp, Ki, are the
predicted workload, measured workload,
proportional coefficient, and discrete integral
(summation) coefficient, respectively. When CPU
utilization is less than unity, workload is
accurately predicted (theorem 1). If utilization
is unity, the workload prediction algorithm is
blind. For this reason, during the speed setting
phase, the speed is set to a value C units
greater than the predicted workload. This forces
the speed to increase until utilization falls and
demand is again equal to the workload.
IV. Experimental Setup
V. Results and Observations
The proposed voltage scaling algorithm was tested
in the context of an embedded-systems simulation
testbed, SimBed. This testbed models the
performance and energy consumption of the
embedded M-CORE microcontroller, a low-power,
32-bit CPU core with 16-bit instructions. It
executes unmodified Motorola binaries compiled
for real hardware and is cycle-accurate to within
1 cycle per 1000 for performance measurements.
For energy consumption estimates, it has been
verified by actual hardware comparison to be
within 10-15 of measured values. NOS (Not an
Operating System)a non-preemptive,
fixed-priority task schedulerwas run on SimBed,
modified to support DVS. Various applications
from the MediaBench benchmark suite were
repetitively scheduled by NOS with periodicity, T
(see figure below). Jitter is defined to be the
deviation from the established period, T, in the
difference between successive completion times of
a given task e.g. jitter for the ith task is Ji
T-(ti(n1)-tin). t1n
t1(n1)
------------------------T-----------------------
task1task2taskn-1taskni
dletask1task2...
------------------nth period-------------------
References Ankush Varma, Brinda Ganesh, Shahrooz
Shahparnia, Mainak Sen, Suchesmita Roy Choudhury,
Lakshmi Srinivasan, and Bruce Jacob.nqPID an
Aggressive Voltage Scaling Policy Using Rate of
Change. University of Maryland. Ankush Varma,
An analysis of Dynamic Voltage Scheduling
Strategies. University of Maryland. May 31,
2002. D. Grunwald, P. Levis, C.B.M III, M.
Neufeld, and K.I. Farkas. Policies for dynamic
clock scheduling. In Proc. Fourth USENIX
Symposium on Operating Systems Design and
Implementation (OSDI2000), San Diego, CA, October
2000, pp. 73-86 Amit Sinha and Anantha P.
Chandrakasan. Dynamic Voltage Scheduling Using
Adaptive Filtering of Workload Traces.
Massachusetts Institute of Technology.
Definitions and theorems offered by Ankush Varma
in An Analysis of Dynamic Voltage Scheduling
Strategies