Reconfigurable Computing

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Reconfigurable Computing

• http//bwrc.eecs.berkeley.edu/Research/BEE

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Reconfigurable Computing for Flexible Radios

• The project grows out of two prior projects
• BEE (Berkeley Emulation Engine)
• BRASS (Berkeley Reconfigurable Architectures,
  Software, and Systems)
• Reconfigurable processors demonstrate 10-100x
  performance improvement over processors.
• Our new project places heavy demands on a new
  computing cluster.

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Berkeley Emulation Engine

• FPGA-based system for real-time hardware
  emulation
• Emulations of ASICs with 10 Million
  gate-equivalents. Corresponds to 600 Gops (16-bit
  adds)
• 2400 external parallel I/Os providing 192 Gbps
  raw bandwidth, for in-system chip emulation.

• Tool-flow maps designs to both FPGA emulation and
  ASIC layout.

• Emulation of
• QPSK radio transceiver, BCJR decoder, UWB
  mix-signal SOC, Pico-radio multi-node system,
  Infineon SIMD processor for SDR

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BEE2 (the new BEE)

• Scaled-up BEE architecture
• Based on state-of-art Xilinx Virtex 2 Pro 100
  FPGA.
• Five FPGAs plus DRAM per processing module.
• Multiple modules (up to 64) wired together with
  high-speed interconnect.
• Extends BEE performance to 75 TeraOp/s and 3
  TFLOP/s range.
• Leverages BEE design experience and tool-flow.
• Collaboration with Xilinx
• Ivo Bolsens, Bob Conn

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BEE2 (the new BEE)

• SDR, Cognitive radio, and Ad-hoc wireless
  networks
• Platform for developing soft-radio techniques,
  validation of network protocols.
• Chip-level validation in context of real data and
  network/environment conditions.
• High-end computing tasks
• Full-chip SPICE simulation, E M simulation for
  antenna design
• Emulation of new reconfigurable architectures and
  programmable ASICs
• Model for future single-chip reconfigurable
  computing architectures
• (BEE2 will be eventually be a single device).

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Unique Characteristics

• Massive parallelism at many levels
• 100 to 1000s of FPGAs, Massive parallelism
  within each FPGA (100K logic blocks).
• Many opportunities for optimal area-time
  tradeoffs.
• Computation normally spreads out in space rather
  than in time.
• Conventional high-end machines have massive
  parallelism only at the course level.
• Low-level circuits customized on a per problem
  basis
• Custom word-width, operator type, hard-wired
  control, custom communication circuits, circuit
  specialization around known constants, etc.

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Unique Characteristics

• Each computing node (FPGA) is customized
  individually.
• Spatial model of computation spreads computation
  modes of problem over nodes of machine, rather
  than in time (phases).
• As opposed to standard SPMD model of
  conventional high-end computers.
• Low-level redundancy of FPGAs allows for
  manufacturing defect tolerance.
• Huge savings in cost - impossible with
  processors.

These characteristics create computational
challenges for the mapping software.
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Tool Flow
HDL circuit spec.
FPGA conf. files
logic synthesis
logic mapping
circuit placement
circuit routing
Xilinx low-level PPR tools

• PPR is time consuming step. Typical run times
  for mapping a design to a large FPGA device is
  several hours.
• Remember, we are planning on 100s of FPGAs.
• Mapping tools are rudimentary (no optimal design
  guaranteed from high-level description), so
  designs are hand-crafted and many iterations of
  tool flow is common.
• Using devices with defects many require multiple
  mapping runs to avoid faults.
• Fortunately, PPR is embarrassingly parallel.
  All chips can be placed and routed in parallel on
  a cluster of workstations.

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Tool Flow

• Eventually, tool flow will be sped up by
• Better high-level specification to optimal
  design, eliminating the need for iteration
  through the flow, and taking advantage of problem
  specific regularity and structure.
• Modular design, reliance on optimized libraries,
• Parallelization of tools Reconfigurable
  computers can someday run their own tools.

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Status

• BEE2 will be fabbricated this summer and will
  become the base of our future work on
  reconfigurable computing
• I/O analog transceivers are being developed to
  allow the implementation of cognitive radios that
  work with real channels and interference

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The BEE2 Team

• Faculty
• John Wawrzynek
• Bob W. Brodersen
• Graduate students
• Chen Chang
• Pierre-Yves Droz
• Nan Zhou
• Yury Markovskiy
• Hayden So
• Kevin Camera
• Zohair Hyder
• Xilinx
• Bob Conn
• Ivo Bolsens

• Research associates
• Andrei Vladimirescu
• Vason Srini
• Technical staff
• Brian Richards
• Susan H. Mellers
• Undergraduate student
• Alexander Krasnov
• Greg Gibeling
• Jeffry West
• John Conner