AVR Logical and Bitwise Instructions

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AVR Logical and Bitwise Instructions

• Assembly Language Programming
• University of Akron
• Dr. Tim Margush

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Boolean Logic

• An algebraic system for Boolean data
• Set false, true)
• Operations and, or , not
• The operations obey certain axioms such as
  associativity, commutativity, identity
• Named after George Boole (1816-1864)
• Implemented via digital logic circuits
  fundamental to the function of a computer

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0 1

• Boolean information is generally represented as 0
  and 1
• Positive logic 0false, 1true
• Each bit therefore represents a Boolean value

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Not

• The Boolean NOT is a unary operator (takes one
  operand)
• The result is the opposite of the input
• A Truth Table is a commonway to define
  Booleanoperations

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AVR's NOT

• The AVR processor's COM instruction applies the
  Boolean NOT to every bit in a register
• com Rd
• Also called the one's complement
• Affects the status register flags

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SREG

• Status Register
• Bits indicating status of processor
• Located in I/O space

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Carry and Zero Flags

• Carry
• This generally indicates a carry out of the most
  significant bit during the addition of two bytes
• Zero
• This indicates when a result is zero
• Z0 when result IS NOT zero
• Z1 when result IS zero

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Negative and oVerflow Flags

• Negative
• This is a copy of bit 7 of the result
• For signed data, it indicates the result is
  negative
• Two's complement oVerflow
• Set (to 1) when an arithmetic operation gives an
  out-of-range result assuming two's complement
  (signed) data

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Half Carry and Sign Flags

• Half Carry
• This usually represents the carry out of the
  first nybble of an addition operation
• Sign
• Indicates the expected sign of a two's complement
  arithmetic operation
• This is always NV (exclusive-or)

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Global Interrupt and Bit Copy

• Global Interrupt enable
• This bit is 1 when interrupts are enabled
• Interrupt signals are ignored while this bit is 0
• Except the reset interrupt
• BiT copy
• Used as a temporary storage location for a single
  bit when using the AVR bit load and bit store
  instruction

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And Or

• The Boolean AND and OR are binary operators (take
  two operands)

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AVR's And Or

• The AVR processor's AND and OR instructions apply
  the Boolean operation to each column of a pair of
  registers
• and Rd, Rr or Rd, Rr
• These affect the status register flags

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Exclusive Or

• The exclusive or operator is commonly defined as
• (a and (not b)) or ((not a) and b)
• It is commonly representedusing the
  symbol,the ? symbol, or theabbreviation xor

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AVR's Exclusive Or

• The AVR processor's EOR instruction applies the
  Boolean operation to each column of a pair of
  registers
• eor Rd, Rr
• This affects the status register flags in the
  same way as the AND and OR instructions

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Immediate Mode

• Immediate mode versions of AND and OR are
  available for registers R16 through R31 only
• andi Rd, k ori Rd, k
• Rd Rd AND k Rd Rd OR k
• The second operand is any expression which is
  assumed to be a byte value
• The byte is coded as part of the instruction

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Using AND

• Common application
• Clear one or more bits in a byte
• Mask
• A byte with 0's in positions to be cleared, 1's
  elsewhere
• Example
• andi R16, 0F clear high nybble
• andi R16, ((1ltlt7) (1ltlt5)) clear bits 7 and 5

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Using AND

• Common application
• Test if one or more bits are set in a byte
• Mask
• A byte with 0's in positions to be ignored, 1's
  in positions to be tested
• Example
• andi R16, 0F test low nybble
• breq allZero branch if low nybble all zeros

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Using OR

• Common application
• Set one or more bits in a byte
• Mask
• A byte with 1's in positions to be set, 0's
  elsewhere
• Example
• ori R16, 0b01100000 set bits 6 and 5
• ori R16, (3ltlt5) same as above

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Using OR

• Common application
• Combining bit fields into one byte
• Preprocessing
• Use ANDI to be sure other bits in the byte are
  cleared
• Example
• andi R16, 0F isolate low nybble
• andi R17, F0 isolate high nybble
• or R16, R17 combine low and high nybbles

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Using EOR

• Common application
• Flip one or more bits in a byte
• Mask
• A byte with 1's in positions to be flipped, 0's
  elsewhere
• Example
• ldi R16, 1ltlt6 mask to flip bit 6
• eor R20, R16 eor has no immediate mode

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Application Letter Case

• Convert characters to upper case
• The only difference between ASCII codes for the
  upper and lower case characters is bit 5
• Uppercase characters bit 5 0
• Lowercase characters bit 5 1
• OR can be used to convert to lower case
• AND can be used to convert to upper case
• EOR can be used to toggle case

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Application ASCII - BCD

• The ASCII codes for the digits have the digits'
  BCD value in the lower nybble.
• All digits have upper nybble 0b0011
• Use AND to convert ASCII to BCD
• Use OR to convert BCD to ASCII

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Packed BCD

• If two BCD digits are to be packed into one byte
• Swap one to the high nybble
• The AVR instruction has a swap instruction
  exactly for this purpose
• Use OR to combine them into one byte

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Other BIT Manipulations

• Set/Clear bits in register
• sbr Rd, k cbr Rd, k
• Only registers 16-31
• k is a byte with 1's in positions to be set or
  cleared
• set means make the selected bit 1, clear means
  make it 0
• You can also do this with ORI or ANDI, in fact,
  these are aliases for
• ori Rd, k andi Rd, k

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Other BIT Manipulations

• Set/Clear bit in I/O register
• sbi A, b cbi A, b
• Only I/O registers 0-31 are accessible with this
  instruction
• The bit number must be 0 through 7
• Note that these instructions affect only 1 bit in
  the register
• No flags are affected by these instructions

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TST

• The TeST instruction affects status flags, but
  does not change any registers
• tst Rd
• This instruction is identical to (an alias for)
  AND Rd, Rd
• Commonly used to see if a register is zero, or
  contains a negative/non-negative value.

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CLR SER

• These instructions clear or set all of the bits
  in a register
• clr Rd (alias for eor Rd, Rd)
• This is really the eor instruction which does
  affect status flags
• ser Rd (alias for ldi Rd, FF)
• Only available for registers 16-31
• The load instructions do not affect flags

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SWAP

• This swaps the two nybbles in a register
• swap Rd
• Does not affect any flags
• This instruction is commonly used in preparation
  for combining two nybble values into a single byte

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Shift

• Shift instructions move bits to adjacent
  positions in a register
• All bits move at the same time and in the same
  direction, left or right
• Left shift or right shift
• What value is used to fill in the vacated spot on
  one end of the register?
• What happens to the bit that falls out of the
  other end of the register?

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LSR, LSL

• These are the logical shifts
• lsr Rd lsl Rd
• The bit brought in is 0
• The bit falling out is copied into the carry flag
• Flags

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ASR

• This is an arithmetic shift
• asr Rd
• The sign bit is preserved (R7 Rd7)
• The lsl instruction is used for an arithmetic
  left shift
• Flags

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ROL ROR

• The rotate instructions use the carry flag to
  determine the bit value in the vacated position
• rol Rd (R0 C) ror Rd (R7 C)
• Flags

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Arithmetic Application

• lsl Rd calculates Rd 2
• Overflow may occur
• Check C for unsigned data
• Check V for signed data
• lsr Rd calculates Rd / 2 (unsigned)
• asr Rd calculates Rd / 2 (signed)
• Rounding is to the left on the number line
• -5 shifted right gives -3 (not -2)

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Application Bit Visiting

• Examining one bit at a time can be accomplished
  in a loop
• Each bit falls into the carry flag where it can
  be tested
• Using rotate, the original data can be preserved

• .def loopcounter R16
• .def databyte R17
• .def bitscounted R18
• clr bitscounted
• ldi loopcounter, 8
• nextbit
• ror databyte
• brcc iszero
• inc bitscounted
• iszero
• dec loopcounter
• brne nextbit
• ror databyte

Next bit to carry flag
Restore original state
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Application Bit Reversal

• Bits from one byte can be rotated into another
  byte an any order
• In this example, the bits are reversed by
  rotating them into a second byte in the opposite
  order

• .def loopcounter R16
• .def databyte R17
• .def reversedbyte R18
• ldi loopcounter, 8
• nextbit
• lsr databyte
• rol reversedbyte
• dec loopcounter
• brne nextbit
• databyte now 00
• reversedbyte has reversed
• copy of original
• databyte

rightmost bit to carry flag then to other byte
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Additional Bit Manipulations

• Because the AVR processor is designed for
  embedded applications with limited memory,
  bit-based data and operations are quite common
• As a result, many specialized bit operations are
  present
• We have already looked at sbr, cbr, sbi, cbi, and
  swap

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BST BLD

• The bit store and bit load instructions allow
  transfers between a single bit of any register
  and the T flag in SREG
• bst Rd, b T Rd(b)
• Note that Rd is not the destination register, but
  it does appear as the first operand of this
  instruction
• bld Rd, b Rd(b) T

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BCLR BSET

• These instructions clear or set a bit in the
  status register (by its position)
• bclr s SREG(s) 0
• bset s SREG(s) 1
• s is a position 0 .. 7
• You will never need these instructions - All have
  a special alias so you do not need to lookup the
  bit number of each flag

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Status Flag Manipulation

• Individual instructions exist to set or clear
  status flags by name instead of position
• These are aliases for the corresponding bclr or
  bset instruction

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Timer/Counters

• The ATMega16 has three timer/counter devices
  on-chip
• Each timer/counter has a count register
• A clock signal can increment or decrement the
  counter
• Interrupts can be triggered by counter events

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8-Bit Timer/Counter
External Clock Signal
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Timer Events

• Overflow
• In normal operation, overflow occurs when the
  count value passes FF and becomes 00
• Compare Match
• Occurs when the count value equals the contents
  of the output compare register

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Output Compare Unit
External Output
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Status via Polling

• Timer status can be determined through polling
• Read the Timer Interrupt Flag Register and check
  for set bits
• The overflow and compare match events set the
  corresponding bits in TIFR
• TOVn and OCFn (n0, 1, or 2)
• Timer 1 has two output compare registers 1A and
  1B
• Clear the bits by writing a 1

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Automatic Timer Actions

• The timers (1 and 2 only) can be configured to
  automatically clear, set, or toggle related
  output bits when a compare match occurs
• This requires no processing time and no interrupt
  handler it is a hardware feature
• The related OCnx pin must be set as an output
  normal port functionality is suspended for these
  bits
• OC0 (PB3) OC2 (PD7)
• OC1A (PD5) OC1B (PD4)

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Timer Clock Sources

• The timer/counters can use the system clock, or
  an external clock signal
• The system clock can be divided (prescaled) to
  signal the timers less frequently
• Prescaling by 8, 64, 256, 1024 is provided
• Timer2 has more choices allowing prescaling of an
  external clock signal as well as the internal
  clock

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ATMega16 Prescaler Unit
External Clock Signals
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Clock Selection

• TCCR0 and TCCR1B Timer/Counter Control Register
  (counters 0 and 1)
• CSn2, CSn1, CSn0 (Bits 20) are the clock select
  bits (n 0 or 1)
• 000 Clock disabled timer is stopped
• 001 I/O clock
• 010 /8 prescale
• 011 /64 prescale
• 100 /256 prescale
• 101 /1024 prescale
• 110 External clock on pin Tn, falling edge
  trigger
• 111 External clock on pin Tn, rising edge
  trigger

• TCCR2 Timer/Counter Control Register (counter
  2)
• CS22, CS21, CS20 (Bits 20) are the clock select
  bits
• 000 Clock disabled timer is stopped
• 001 T2 clock source
• 010 /8 prescale
• 011 /32 prescale
• 100 /64 prescale
• 101 /128 prescale
• 110 /256 prescale
• 111 /1024 prescale
• ASSR (Asynchronous Status Register), bit AS2 sets
  the clock source to the internal clock (0) or
  external pin TOSC1)

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Timer Modes

• Normal Mode
• Counter counts up,
• TOV occurs when it reaches 0
• Clear Timer on Compare Mode (CTC)
• Counter counts up to match the Output Compare
  Register
• On the next count, it resets to 0 and the OC Flag
  is set

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Timer Modes

• Fast PWM (Pulse Width Modulation) Mode
• Counter counts from BOTTOM to MAX and resets
• Inverting mode OC is cleared at BOTTOM and set
  at match
• Non-Inverting Mode OC is set at BOTTOM and
  cleared at match

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Timer Modes

• Phase Correct PWM Mode
• Counter counts from BOTTOM to MAX , then reverses
• OC is changed when the count matches the OCR
  value
• Inverting mode OC is cleared while downcounting,
  set while upcounting
• Non-Inverting Mode OC is cleared while
  upcounting, set while downcounting

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Timer Control (Timer0)

• WGM010 Waveform Generation Mode
• 00 Normal
• 01 PWM
• 10 CTC
• 11 Fast PWM
• Clock Select
• covered previously

• Compare Match Output Mode
• 00 Nothing
• 01 Toggle
• 10 Clear
• 11 Set
• Behavior is slightly different in each WG mode

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Timer Count Value

• The timer's current value may be read or written
  at any time
• in R16, TCNT0 out TCNT0, R17
• The output compare function is disabled for one
  cycle after a write
• Modification while the timer is running may also
  cause a missed compare

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Output Compare Register

• OCR0 holds a byte that is constantly compared to
  the TCNT0 value
• Matches can cause several actions
• Output compare interrupt
• Or just setting the output compare flag
• Generate a waveform on OC0
• Cause a timer reset (TOP)

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Flags

• TIFR - Timer/Counter Interrupt Flags
• Output Compare Flag
• Timer Overflow Flag
• Input Capture Flag

Timer 0 flags
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Timer 0 Switch Debounce

• Use Timer/Counter 0 to measure a 10 millisecond
  interval each time the switch data changes
• Debouncing is accomplished by ignoring switch
  data during this interval
• We must store the last known switch data between
  calls.
• Function will return switch data once for each
  press/release, at the instant of the release

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• byte switchread()
• static byte state FF
• byte currentswitches
• if (timer running) return FF ignore everything
• currentswitches switches read switch data
• if (state ! currentswitches) if different from
  previous, start blackout period
• start timer
• if (currentswitches!FF) this is not a release
  event, so just store state
• state currentswitches
• currentswitchesFF return no switch data
• else this is a release event
• currentswitches state return stored state
• state FF record release
• return currentswitches
• else
• return FF same, return no switch data