Liveness Analysis

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Liveness Analysis

• Mooly Sagiv
• Schrierber 317
• 03-640-7606
• Wed 1000-1200
• html//www.math.tau.ac.il/msagiv/courses/wcc.html
  

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Already Studied
Source program (string)
lexical analysis
Tokens
syntax analysis
Abstract syntax tree
semantic analysis
Abstract syntax tree
Translate
Tree IR
Cannon
Cannonical Tree IR
Instruction Selection
Assem (with many reg)
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Register Allocation

• Input
• Sequence of machine code instructions(assembly)
• Unbounded number of temporary registers
• Output
• Sequence of machine code instructions(assembly)
• Machine registers
• Some MOVE instructions removed
• Missing prologue and epilogue

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LABEL(l3) CJUMP(EQ, TEMP t128, CONST 0, l0,
l1) LABEL( l1) MOVE(TEMP t131, TEMP
t128) MOVE(TEMP t130, CALL(nfactor, BINOP(MINUS,
TEMP t128, CONST 1))) MOVE(TEMP t129,
BINOP(TIMES, TEMP t131, TEMP t130)) LABEL(l2) MOV
E(TEMP t103, TEMP t129) JUMP(NAME
lend) LABEL(l0) MOVE(TEMP t129, CONST
1) JUMP(NAME l2)
Missing updates for static link
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l3 beq t128, 0, l0 l1 or t131, 0,
t128 addi t132, t128, -1 or 4, 0, t132 jal
nfactor or t130, 0, 2 or t133, 0,
t131 mult t133, t130 mflo t133 or t129, 0,
t133 l2 or t103, 0, t129 b lend l0 addi
t129, 0, 1 b l2
l3 beq 25, 0, l0 l1 or 30, 0, 25 addi
4, 25, -1 / or 4, 0, 4
/ jal nfactor / or 2, 0, 2
/ / or 30, 0, 30 / mult 30,
2 mflo 30 / or 30, 0, 30 / l2
or 2, 0, 30 b lend l0 addi 30, 0,
1 b l2
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.global nfactor .ent nfactor factor_fram
esize40 .frame sp,nfactor_framesize,31 nfactor
addiu sp,sp,-nfactor_framesize
sw 2,0nfactor_framesize(sp) or 25, 0, 4
sw 31,-4nfactor_framesize(sp)
sw 30,-8nfactor_framesize(sp)
l3 beq 25, 0, l0 l1 or 30, 0, 25 addi
4, 25, -1 jal nfactor mult 30, 2 mflo
30 l2 or 2, 0, 30 b lend l0 addi 30,
0, 1 b l2
lend lw 30,-8nfactor_framesize(sp)
lw 31,-4nfactor_framesize(sp)
addiu sp,sp,nfactor_framesize j 31
.end nfactor
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The need for spilling

• The number of registers may not be enough
• Spill the content of some registers into memory
• Load when needed
• Increase the number of instructions
• Slower the generated code

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The Challenge

• Minimize the number of spills
• Minimize the number of MOVEs
• Minimize CPU time

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Outline

• Liveness Analysis
• Motivation
• Static Liveness
• Dataflow Equations
• Solutions
• An Iterative Algorithm
• Liveness in Tiger (Targil)
• Actual Allocation

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Liveness Analysis

• The same register may be assigned (at
  compile-time) to two temporaries if their
  life-times do not overlap
• A variable is live at a point in a givenprogram
  point
• if its current value is used after this point
  prior to a definition
• Two variables interfere at a given point
• they are simultaneously live at this point

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A Simple Example
/ c / L0 a 0 / ac / L1 b a
1 / bc / c c b / bc / a b 2 /
ac / if c lt N goto L1 / c / return c
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Liveness Interference Graph

• For every compiled function
• Nodes
• Pre-colored machine registers
• Temporaries
• Undirected-Edges
• Temporaries that are simultaneously alive
• Different machine registers
• Undirected MOVE edges
• Correlated temporaries and registers

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Other usages of Livness
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A Simple Example
/ c / L0 a 0 / ac / L1 b a
1 / bc / c c b / bc / a b 2 /
ac / if c lt N goto L1 / c / return c
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l3 beq t128, 0, l0 / 0, t128 / l1 or
t131, 0, t128 / 0, t128, t131 / addi t132,
t128, -1 / 0, t131, t132 / or 4, 0, t132
/ 0, 4, t131 / jal nfactor / 0, 2,
t131 / or t130, 0, 2 / 0, t130, t131
/ or t133, 0, t131 / 0, t130, t133 / mult
t133, t130 / 0, t133 / mflo t133 / 0,
t133 / or t129, 0, t133 / 0, t129 / l2
or t103, 0, t129 / 0, t103 / b lend
/ 0, t103 / l0 addi t129, 0, 1 / 0,
t129 / b l2 / 0, t129 /
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Undecidabily

• A variable is live at a point in a givenprogram
  point
• if its current value is used after this point
  prior to a definition in some execution path
• It is undecidable if a variable is live at a
  given program location

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Proof Sketch
Pr L x y
Is y live at L?
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Conservative

• The compiler need not generate the optimal code
• Can use more registers (spill code) than
  necessary
• Find an upper approximation of the live variables
• A superset of edges in the interference graph
• Not too many superfluous live variables

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Control Flow Graph

• Nodes
• Assembly instructions
• Directed-Edges
• If an instruction x can be immediately followed
  by an instruction y
• A directed edge x?y

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Static Liveness

• A variable v is statically live at control flow
  node n
• there exists a directed path p from n to a use of
  v such that
• p does not include an assignment to v
• Every live variable is statically live
• Some statically live variables are not live
• since some control flow paths are non-executable

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Example
a b b
a b b c a b if (c gt b) then
return c else return a
c a b
c gt b
return c
return a
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a 0
/ c / L0 a 0 / ac / L1 b a
1 / bc / c c b / bc / a b 2 /
ac / if c lt N goto L1 / c / return c
b a 1
c c b
a b2
c ltN goto L1
return c
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Computing Static Liveness

• Generate a system of equations for every function
• define the set of live variables recursively
• Iteratively compute a minimal solution

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The System of Equations

• For every instruction n
• defn
• The temporary and physical register(s) assigned
  by n
• usen
• The temporary and physical register used in n
• System of equations
• LiveOutex ?
• LiveOutn ? (n, m) ? Edges Livem
• Liven (LiveOutn defn) ? usen

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ins defn usen
1 a ?
2 b a
3 c c, b
4 a b
5 ? c
6 ? c
LiveOut6 ? Live6 (LiveOut6 ?) ?
c LiveOut5 Live6 ? Live2 Live5
(LiveOut5 ?) ? c LiveOut4 Live5
Live4 (LiveOut4 a) ? b LiveOut3
Live4 Live3 (LiveOut3 c) ? c,
b LiveOut2 Live3 Live2 (LiveOut2
b) ? a LiveOut1 Live2 Live1
(LiveOut1 a) ? ?
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ins defn usen
1 a ?
2 b a
3 c c, b
4 a b
5 ? c
6 ? c
LiveOut6 ? Live6 LiveOut6 ?
c LiveOut5 Live6 ? Live2 Live5
LiveOut5 ? c LiveOut4 Live5 Live4
(LiveOut4 a) ? b LiveOut3
Live4 Live3 (LiveOut3 c) ? c,
b LiveOut2 Live3 Live2 (LiveOut2
b) ? a LiveOut1 Live2 Live1
(LiveOut1 a)
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Fixed Points

• A fixed point is a vector solution Live and
  LiveOut
• for every instruction n
• LiveOutex ?
• LiveOutn ? (n, m) ? Edges Livem
• Liven (LiveOutn defn) ? usen
• There more than one fixed pint
• Every fixed point contains at least the
  statically live variables
• The least fixed point (in terms of set
  inclusion) uniquely exists
• it contains exactly the statically live variables

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LiveOut6 ? Live6 LiveOut6 ?
c LiveOut5 Live6 ? Live2 Live5
LiveOut5 ? c LiveOut4 Live5 Live4
(LiveOut4 a) ? b LiveOut3
Live4 Live3 (LiveOut3 c) ? c,
b LiveOut2 Live3 Live2 (LiveOut2
b) ? a LiveOut1 Live2 Live1
(LiveOut1 a)
ins LiveOut Live
1 c, a c
2 c, b c, a
3 c, b c, b
4 c, a c, b
5 c,a c, a
6 ? c
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LiveOut6 ? Live6 LiveOut6 ?
c LiveOut5 Live6 ? Live2 Live5
LiveOut5 ? c LiveOut4 Live5 Live4
(LiveOut4 a) ? b LiveOut3
Live4 Live3 (LiveOut3 c) ? c,
b LiveOut2 Live3 Live2 (LiveOut2
b) ? a LiveOut1 Live2 Live1
(LiveOut1 a)
ins LiveOut Live
1 c, a, d c, d
2 c, b, d c, a, d
3 c, b, d c, b, d
4 c, a, d c, b, d
5 c,a, d c, a, d
6 ? c
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LiveOut6 ? Live6 LiveOut6 ?
c LiveOut5 Live6 ? Live2 Live5
LiveOut5 ? c LiveOut4 Live5 Live4
(LiveOut4 a) ? b LiveOut3
Live4 Live3 (LiveOut3 c) ? c,
b LiveOut2 Live3 Live2 (LiveOut2
b) ? a LiveOut1 Live2 Live1
(LiveOut1 a)
ins LiveOut Live
1 c, a, b c, b
2 c, b c, a
3 c, b c, b
4 c, a c, b
5 c,a c, a
6 ? c
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LiveOut6 ? Live6 LiveOut6 ?
c LiveOut5 Live6 ? Live2 Live5
LiveOut5 ? c LiveOut4 Live5 Live4
(LiveOut4 a) ? b LiveOut3
Live4 Live3 (LiveOut3 c) ? c,
b LiveOut2 Live3 Live2 (LiveOut2
b) ? a LiveOut1 Live2 Live1
(LiveOut1 a)
ins LiveOut Live
1 c, a c
2 c, b c, a
3 c, b c, b
4 c c, b
5 c c
6 ? c
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An Iterative Algorithm
WL ? for each instruction n LiveOutn
? Liven ? WL WL ? n while WL ! ?
select and remove n from WL new
(LiveOutn defn) ? usen if new !
Liven then Liven new for all
predecessors m of n do
LiveOutm LiveOutm ? Liven
WL WL ?m
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n Liven LiveOut WL
6, 5, 4, 3, 2, 1
6 c LiveOut5c 5, 4, 3, 2, 1
5 c LiveOut4c 4, 5, 2, 1
4 c, b LiveOut3c,b 3, 2, 1
3 c, b LiveOut2c,b 2, 1
2 c, a LiveOut1c,a LiveOut5c,a 5, 1
5 c, a LiveOut4c,a 4, 1
4 c, b 1
1 c ?
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Representation of Sets

• Bit-Vectors
• Var bits for every n
• Livenv 1
• the variable v is live before n
• Cost of set operation is
• O(Vars/word-size)
• Ordered Elements
• Linear time for set operations

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Time Complexity

• Parameters
• N number of nodes (instructions)
• Assume that predn is constant
• V Number of variables
• d Number of loop nesting level
• DFS back edges
• Initialization NV
• Inner-Most Iteration V
• For-Loop N
• Repeat
• Worst-Case NV
• Worst-Case-DFS d 1
• Total-Worst-Case (NV)2
• Total-DFS NVd
• Single-variable N

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An Interference Graph
for every instruction n for every variable a?
defn for every variable b ? LiveOutn
Create an interference edge
b
a
May introduce too many edges for move
instructions
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Example
t s x s y t
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An Interference Graph
for every non move instruction n for every
variable a? defn for every variable b ?
LiveOutn Create an interference edge
b
a
for every move instruction n a c for every
variable b ? LiveOutn c Create an
interference edge
b
a
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A Simple Example
/ c / L0 a 0 / ac / L1 b a
1 / bc / c c b / bc / a b 2 /
ac / if c lt N goto L1 / c / return c
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l3 beq t128, 0, l0 / 0, t128 / l1 or
t131, 0, t128 / 0, t128, t131 / addi t132,
t128, -1 / 0, t131, t132 / or 4, 0, t132
/ 0, 4, t131 / jal nfactor / 0, 2,
t131 / or t130, 0, 2 / 0, t130, t131
/ or t133, 0, t131 / 0, t130, t133 / mult
t133, t130 / 0, t133 / mflo t133 / 0,
t133 / or t129, 0, t133 / 0, t129 / l2
or t103, 0, t129 / 0, t103 / b lend
/ 0, t103 / l0 addi t129, 0, 1 / 0,
t129 / b l2 / 0, t129 /
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Summary

• The compiler can statically predict liveness of
  variables
• May be expensive
• Other useful static information
• Constant expressions
• Common sub-expression
• Loop invariant
• Liveness inference graph will be colored next
  meeting