Computer Organization and Assembly Language

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80286

• 80286 ???????????????? 8 MHz
• ???????? task switching ???
• ???????????????????????????????????? ( Memory
  Management )
• Address Bus 24 ???? ?????????????????? 16 MB
• ?? Virtual Memory ??? 1 GB / Task
• ??? Address Bus ??? Data Bus ?????????????????????
  ???
• ????? 80286 ???????????? ???????????????? PGA
  (Pin Grid Array) ??? LCC ( Lead Chip Carrier )
• Backward Compatible ??? 8088

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Computer Organization and Assembly Language 7
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80286 Pin Out
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Computer Organization and Assembly Language 7
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Protect Mode

• 80286 has 2 modes Real and Protect mode
• DOS can not run on protect mode
• For backward Compatible Real mode must be use
• First start on Real mode after reset
• And switch to Protect mode when desire

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Computer Organization and Assembly Language 7
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Protect Mode

• ??????? Memory ??????? 1 MB
• No Segment in Protect mode
• Segment register has change to Selector
• Selector use to select Description Table (
  Descriptor )
• Descriptor has information of
• Address of Memory
• Length
• Access Right

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Computer Organization and Assembly Language 7
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Descriptor
13 Bit 8,192 Descriptor
TI 0 mean Global Descriptor ( GDT ) TI 1 mean
Local Descriptor ( LDT ) RPL Request Privilege
Level 0, 1, 2 and 3
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Computer Organization and Assembly Language 7
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Memory Space of 3 Tasks
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Address Space of Tasks

• Local Address Space
• 8,192 ???? ???????????? Local Descriptor 1
  ???????
• ????????????????? 64 KB
• 8,192 X 64 KB 512 MB
• Global Address Space
• 8,192 ???? ???????????? Local Descriptor 1
  ???????
• ????????????????? 64 KB
• 8,192 X 64 KB 512 MB
• 1 Task 1 LDT 1 GDT 1 GB
• 1 GB is Virtual memory

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Descriptor Table
Access rights 8 Bits Base Address 24 Bits 16
MB of Memory Limit 16 Bits 64 KB of Memory
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Computer Organization and Assembly Language 7
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Descriptor Table
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LDT, GDT and IDT

• LDT code and Memory of each Application
• GDT code and information of OS and its
  service
• IDT (Interrupt Descriptor Table) ISR address
• LDTR, GDTR and IDTR ( Pointer )
• Only LDTR has Access Rights
• IDTR and GDTR have 40 Bits ( No access right )
• IDTR and GDTR length are constant, cos only one
  table
• Length of LDTR change every time that load task
• Information of LDT keep in GDT

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Computer Organization and Assembly Language 7
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Memory protection in 80286

• 80286 has memory protection
• 4 Privilege level 0, 1, 2 and 3
• 0 is highest priority
• In selector we have RPL bit
• RPL Request Privilege Level
• In LDTR, Access right has DPL field
• DPL Descriptor Privilege Level
• ( Level of memory segement)

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Computer Organization and Assembly Language 7
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Memory protection in 80286
Present Bit 1 mean Descriptor not
use Accessed 1 mean Descriptor has been load
to Descriptor Reg. Readable 0 mean Program
from other segment cant call program on this
segment Conforming 1 mean Only same privilege
can call procedure Writable 1 mean Can write
this segment Expansion-Direction 0 mean
Ascending ( Data segment ) 1 mean Descending
( Stack segment )
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Computer Organization and Assembly Language 7
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Multitasking

• 80286 has Multitasking ability
• All task has its own program environment (
  Register and Memory )
• Must be run in Protected mode
• Task in memory call Process
• All task has processing time
• Protect task failure by OS, if some task have
  failed not effect other

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Computer Organization and Assembly Language 7
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Task State Segment ( TSS )

• TSS One Special Segment use to keep register,
  Selector and LDT
• One TSS per task
• TSS Descriptor keep all TSS
• Run one task only point by Task Register ( 16
  Bits )
• Change task by instruction Jmp or Call
• Before change task must save TSS of old task and
  load new task later

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Computer Organization and Assembly Language 7
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Kernel and User mode

• Kernel mode is in ring 0
• Application is in User mode ( Ring 1, 2 and 3)

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Computer Organization and Assembly Language 7
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Pipeline in 80286

• 4 stages of pipeline
• Instruction unit
• Execution unit
• Address unit
• Bus unit

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Computer Organization and Assembly Language 7
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80386

• 32 Microprocessor
• 32 Bits on Register, Data bus and Address bus
• Maximum memory is 4 GB
• Paging technology for Protected mode
• 64 TB on Paging technique

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Computer Organization and Assembly Language 7
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80386 Register
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80386 Descriptor
Base change to 32 Bits 4 GB of Memory
space Limit change to 20 Bit 1 MB of
Segment Granularity ( G ) 1 mean Limit count
by 4K Available ( AV ) 0 mean Available, Use
by OS D 0 mean use register 16 bits ( as in
80286), 1 mean use register 32 bits
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Computer Organization and Assembly Language 7
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80386
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Computer Organization and Assembly Language 7
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Multiprocessing in 80386

• New feature of Memory Management in 80386
• Virtual 8086 mode
• Emulate 8086 more than 1 unit in 80386
• With 1 MB each
• Work in parallel ( Multiprocessing )

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Computer Organization and Assembly Language 7
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80486

• 80286 have Protect and real mode
• 80386 is 32 bits with Virtual 8086 mode
• 80486 new feature
• new pipeline with 5 stage
• Fetch, Decode1, Decode2, Execute and Write back
• 1 clock 1 instruction
• 8 KB cache L1
• integrated 80387 Math-Coprocessor
• 1st CPU with 1 million transistor
• Fabrication on 0.8 Micron technology
• with speed 33 MHz, 15-20 MIPS

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Computer Organization and Assembly Language 7
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Pentium

• 64 Bits data bus
• Separate Instruction Cache and Data Cache
• difference behavior
• Superscalar architecture ( 100 MIPS )
• Enhance FPU
• 1st CPU with 3 million transistor
• 20 Watts power consumption ( new version is 3.3
  V)
• Biggest die, cos fabrication on 0.8 micron ( new
  version is 0.18 )

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Pentium
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Pentium

• Superscalar technique
• Prefetcher read opcode from Instruction Cache
• ( 8K ) via 256 bits bus
• 64 bits of Prefetch buffers on each pipe
• With Branch prediction on each Prefetch buffer
• When execute on branch instruction, BTB
• ( Branch Target Buffer )
• Switch the right Prefetch buffer
• 2 Decoder unit Opcode and Address
• 2 ALU U and V ALU with 1 FPU ( 8 stages of
• pipeline )

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Computer Organization and Assembly Language 7
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Pentium

• More than 1 instruction per clock
• In D1 pipe, Compare instruction in U and Pipe
• Is it dependence?, If not ( Paired ) go ahead
• If dependence, Move from V pipe to U pipe
• ( Main pipe )
• Good architecture, But not useful
• ( Data hazard ), Fixed in P6

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Computer Organization and Assembly Language 7
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Code optimization
mov eax, source /I1 ???????? source ??
eax add eax, ebx /I2 eax eax
ebx instr1... /I3
????????????????????????????? instr2...
/I4 eax, ebx ???
source instr3...
/I5   U PIPE
V PIPE mov eax,
source instr1...
instr2...
instr3... add eax,ebx
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Computer Organization and Assembly Language 7
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Branch Prediction

• Note
• not from Intel,
• but from reverse engineering
• If has two loop, such as Delay loop
• How to predict each loop ?

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Computer Organization and Assembly Language 7
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Two-level Branch Prediction

• Pentium MMX
• Pentium Pro
• Pentium II
• Pentium III

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Pentium pipeline

• 5 stages
• U and V unit
• Execution unit must
• check data in cache
• ( Hit / Miss )

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MMX

• Multimedia Extension ( But Intel not accept this
  )
• Add instruction for multimedia
• 4.5 Million transistor
• Same 80 bits FPU register ( But MMX use only 64
• bits name MM0 MM7 )
• 8 of Packeted bytes
• 4 of Packeted words
• 2 of Packeted double words
• 1 of Packeted quad word
• With new 57 instructions ( start with P ex PADDB
  )
• SIMD instruction ( Single Instruction Multiple
  Data )

C. Vongchumyen 1 / 2004
Computer Organization and Assembly Language 7