Parameterized IP Infrastructures for Fault-Tolerant FPGA-Based Systems:

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National Aerospace University named after N.E.
Zhukovsky "Kharkov aviation institute"
Computer Systems and Networks Department Scientif
ic - Technical Center DeSSerT Dependable
Systems, Services Technologies
Parameterized IP Infrastructures for
Fault-Tolerant FPGA-Based Systems Development,
Assessment, Case-Study
Kulanov Vitaliy Kharchenko Vyacheslav Perepelitsyn
Artem
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EWDTS2009, Moscow
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Outline
1. Fault-tolerance I-IP parameterization
technique 2. Parameterized I-IP Design for
Fault-Tolerant Systems 3. Case-study 4.
Development and Assessments Results
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Introduction
Infrastructure IPs (I-IPs) do not implement new
operations, but support system at a preset level
of functionality and lifetime reliability.

• Some I-IP examples
• Embedded Memory Test and Repair
• Diagnosis
• Timing Measurement
• Process Monitoring
• Fault Tolerance

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Motivation

• Fault-tolerant I-IP parameterization necessity
• I-IP Must Meet In-System Reconfigurability
• Due to the IP parameterization and target system
• reconfiguration
• System Fault-Tolerance Strategy Support
• Different fault-tolerant form of N-modular
  redundancy
• Faster Time-to-Market
• As a part of a target system
• Cost Effectiveness Solution.

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Goals

• The goal of the report
• I-IP parameterization technique overview for
• fault-tolerant FPGA-based projects
• Parameterized I-IP development and
• assessments results for fault-tolerant
• Airborne Ice Protections System control unit

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Fault-Tolerant I-IP Parameterization
I-IP parameter types for fault-tolerant systems

• Functional parameters
• Bus Width
• Memory (Buffer) Size
• .

• Structural (Architectural)
• parameters
• Fault-Tolerant Architecture
• Type (TMR, DMR, )
• Redundant Channels
• Version Implementation
• (Multiversion Design Approach)

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I-IP Parameterization (Cont.)
Functional I-IP Parameter example
D
N
Input Data
Output Data
Functional IP Block
D
Error
K
L
Output Predictor
N, K, D, L bus width parameters
I-IP must meet in-system reconfigurability N
K, D L K, L functional I-IP parameters
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I-IP Parameterization (Cont.)
Structural (Architectural) I-IP Parameter Example
Input Data
V1IP
V2IP
V3IP
V1IP? V2IP? V3IP
Voting Unit
Multiversion Design Approach
Retry
Secure Output

• Fault-Tolerant Architecture Type (e.g. TMR, DMR,
  )
• Redundant Channels Version Implementation
• e.g. V1IPV2IPV3IP or V1IP? V2IP?
  V3IP

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Parameterized I-IP Design for
Fault-Tolerant Systems

• Depends on
• In-system reconfigurability of a fault-tolerant
• system
• System requirements to fault-tolerance
• CAD Tools features
• HDLs features

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Parameterized I-IP Design for
Fault-Tolerant Systems (Cont.)

• I-IP Parameterization in VHDL (ANSI/IEEE Std
  1076-1993)
• GENERIC section
• GENERATE statements
• - FOR-scheme
• - IF-scheme
• CONFIGURATION specification

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Case-study
Airborne Ice Protection System (AIPS) control
unit design with I-IP parameterization approach
in VHDL

• 1. Functional parameters
• Operational frequency
• Measured temperature range
• Heating elements turn-on time characteristics
• 2. Structural (architectural) parameters
• Number of redundant channels (DMR, TMR,
  Pair-And-A-Spare Scheme, Quinary)
• Redundant channels version implementation
• (Two versions)

I-IP parameters
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Development
AIPS Control Unit Fault-Tolerant Architectures
Dual Modular Redundancy
Triple Modular Redundancy
Quinary
Pair-And-A-Spare Scheme
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Development
AIPS Control Unit Multiversion Design Approach
Language Diversity
External Diversity (Different HDLs) e.g. VHDL,
Verilog
Internal Diversity (One HDL)
Different Algorithm
Different Language Constructs
Number of AIPS Control Unit Versions 2
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Assessments Results

• AIPS Control Unit Project Evaluation Metrics
• Project Resource Utilization
• (Number of Logic Elements (LE))
• Probabilities of up state for different I-IP
  Architectures

• CAD Tool and HDL
• Quartus II Web Edition 9.1
• VHDL (ANSI/IEEE Std 1076-1993)

• Hardware Platform
• Cyclone Device Family

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Assessments Results (Cont.)
FPGA Resource Utilization For Different I-IP
Architectures
Number of LE
DMR
TMR
Pair-And-A-Spare
Quinary
V1 Version 1 V2 Version 2
- Remove Duplicate Register option turned off
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Assessments Results (Cont.)
Failure rate of different I-IP architectures
?, ? FPGA I/O and service resources reliability
coefficients
Probabilities of up state for one channel (IP)
and I-IP architecture
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Assessments Results (Cont.)
Probabilities of up state for Different I-IP
Architectures
P(t)
t
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Conclusions and Future Work

• Conclusions
• A multiversion design approach with language
• diversity has a great influence on system
  resource
• utilization of a chip
• Pair-And-A-Spare scheme and TMR architecture
• have better up state probability

• Problems that should be solved
• Fault-tolerance I-IP synchronization problem for
  
• complex projects

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National Aerospace University named after N.E.
Zhukovsky "Kharkov aviation institute"
Computer Systems and Networks Department
Thank You!
Scientific - Technical Center DeSSerT
Dependable Systems, Services
Technologies http//stc-dessert.com
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EWDTS 2009