FPGA Lab

1
An Entropy-based Learning Hardware Organization
Using FPGA
Janusz Starzyk and Yongtao Guo March 19, 2001

• FPGA Lab
• School of Electrical Engineering and Computer
  Science
• Ohio University, Athens, OH 45701, U.S.A.

2
Outline

• Introduction
• Entropy-based Evaluator
• Hardware Implementation
• Synthesis Performance
• Summary

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Introduction

• WHAT ARE NEURAL NETWORKS ?
• Main function
• Like human brain
• FEATURES OF NEURAL NETWORKS ?
• Self-Organizing Learning.
• Fault tolerant.
• Fast run but not fast to learn.
• Particularly suited to problems.
• Can be trained to generate non-linear mappings.

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Introduction --Self Organizing Learning

• Feed-forward (FF)
• Threshold-controlled input (TCI)
• Threshold-controlled outputs (TCO)
• Entropy based evaluator
• Information deficiency

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Entropy-based Evaluator

• Entropy based information index

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Entropy-based Evaluator

• Subspaces information deficiency

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Entropy-based Evaluator - Information Index

• Necessary Approximation
• Mult(a,b)E(Sub(L(a)L(b),B)) multiplication
• Divd(a,b)E(Sub(L(a),L(b))) division
• L(a) returns the location (starting from 0) of
  the most significant bit position of a,
• E(a) forces 1 on a-th bit position ( a
  modification of this operation forces 1 on
  a, a-2, a-4 etc. bit positions).
• B word length

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Entropy-based Evaluator - Structural Simulation
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Entropy-based Evaluator - VHDL Design
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Entropy-based Evaluator - VHDL Simulation at
RTL
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Hardware Implementation

• EBE hardware model
• Memory circuit (LUT)
• Comparator unit
• ECU
• Two registers

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Hardware Implementation
- ECU Architecture
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Hardware Implementation

• Other components
• Control Unit
• System clock, state transfer signals,
  handshake signals.
• MUX DMUX
• Parallel process of the multi-feature data
  in the input classes.
• Display Unit
• Real-time monitor for the data transfer.
• EBE Interface
• Between FIFO control unit, PCI bus and EBE for
  rapid data transfer and easy online system
  debugging.

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Hardware Implementation
Output
Figure- FPGA-based Architecture
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Hardware Implementation

• Reconfigurable Advantage
• Exploit cases where operation can be bound and
  then reused a large number of times.
• Customization of operator type, width, and
  interconnect.
• Flexible low overhead exploitation of application
  parallelism.

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Synthesis Performance -Implementation Flow
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Synthesis Performance --Map design to Virtex
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Synthesis Performance --FPGA Map
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Synthesis Performance --Schematic
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Synthesis Performance --FPGA Floorplan
Vendor Xilinx Family VIRTEX Device
V800BG432 Speed -4 Number of External GCLKIOBs
1 out of 4 25 Number of External
IOBs 47 out of 316 14 Number
of BLOCKRAMs 4 out of 28
14 Number of SLICEs 463
out of 9408 4 Number of DLLs
1 out of 4 25 Number of
GCLKs 1 out of 4
25 Number of TBUFs
256 out of 9632 2 Number of flip-flops
336 Minimum period
24.838ns Maximum frequency
40.261MHz Total equivalent gate
count for design 88,186 Additional JTAG gate
count for IOBs 2,304
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Summary
 

• Self-Organizing Algorithm
• Matlab VHDL Simulation
• Hardware Architecture
• Synthesis
• Analog Circuits