FPGA System Design with Verilog

1
FPGA System Design withVerilog

• A Workshop Prepared for Rose-Hulman Ventures
• Ed Doering

2
Workshop Goals

• Gain familiarity with FPGA devices
• Gain familiarity with HDL design methods
• Implement basic designs in hardware

3
Agenda
FPGA Overview 830 - 915
Verilog Overview 915 - 1000
Combinational Circuits 1015 - 1100
Lab Projects I 1100 - 1200
Sequential Circuits 115 - 200
Lab Projects II 200 - 300
Lab Projects III 315 - 400
4
FPGA Overview
5
What is an FPGA?

• Field Programmable Gate Array
• Blank slate for your digital hardware system

6
FPGA in Context

• Microprocessor/microcontroller
• Executes a program
• Fixed hardware and interconnections
• Full-custom IC
• Design at the transistor level

7
FPGA in Context

• Semicustom IC
• Standard cell (CBIC, ASIC)
• Masked gate array (MGA)
• Programmable logic device (PLD)
• PLD
• Complex PLD (CPLD)
• FPGA

8
When to Use an FPGA

• Design economics
• Shortest time to market
• Lowest NRE cost
• Highest unit cost
• Make quick grab for market share, then do cost
  reduction with ASICs

9
FPGA Pictures

• Board
• Packages
• Wafer
• Die photos
• FPGA
• Pentium II microprocessor

Sources http//www.xilinx.com/company/press/produ
cts/pictures2.htm, http//micro.magnet.fsu.edu/chi
pshots/pentium/
10
Internal Architecture

• Array of Configurable Logic Blocks (CLBs)
• User-defined (SRAM-based) interconnect between
  CLBs
• Dedicated resources
• Power distribution
• Clock distribution
• Programmable I/O blocks (IOBs)

11
Configurable Logic Block
Source Smith, M.J.S., Application-Specific
Integrated Circuits,Addison-Wesley, 1997.
12
Programmable I/O Block
Source Smith, M.J.S., Application-Specific
Integrated Circuits, ddison-Wesley, 1997.
13
PLD Vendors
Source Xilinx University Program Workshop Notes
14
Xilinx FPGA Product Families

• Virtex-II (Platform FPGA, 10M gates)
• Virtex (1M gates), Virtex-E (3M gates)
• Spartan (low cost ASIC replacement)
• XC4000 (first FPGA family, now with enhancements)

15
Altera FPGA Product Families

• APEX-II (up to 7M gates)
• APEX20K (up to 1.5M gates)
• Mercury (ASIC replacement, ASSP)
• FLEX 10K

16
Hybrid FPGA / Microcontroller

• Triscend E5 CSoC (configurable system-on-chip)
• 8-bit 8051-based microcontroller
• 40K system gates
• Triscend A7 CSoC
• 32-bit ARM7TDMI processor
• 40K system gates

17
Hybrid FPGA / Microcontroller

• Atmel FPSLIC (Field Programmable System-Level
  Integrated Circuit)
• 5K to 40K system FPGA gates
• 8-bit AVR RISC microprocessor core
• Microcontroller peripherals
• 36K program and data RAM

18
Choosing CPLD or FPGA

• CPLD
• Nonvolatile (ROM- or EEPROM-based)
• Predictable delays (no routing)
• Register poor (relatively few FFs)
• Low-to-medium density
• For simple, fast logic with many inputs
• Specialized decoders, combinational circuits,
  counters

19
Choosing CPLD or FPGA

• FPGA
• Volatile (SRAM-based)
• Configuration must be stored externally (serial
  EEPROM)
• Permits field upgrades, reconfigurable computing
• Variable routing delays
• Register rich (relatively many FFs)
• For arbitrary digital systems, system-on-chip
  (SoC), medium-to-high density

20
Verilog Overview
21
Hardware Description Languages

• Verilog
• Gateway Design Automation (1983 proprietary)
• Acquired by Cadence 1989
• IEEE standard in 1995
• Similar to C

• VHDL
• Origins in DoD VHSIC program (1980s)
• IEEE standard in 1987
• Similar to ADA

22
Verilog vs. VHDL

• Verilog is less wordy
• Industry is about 50-50
• VHDL more common in adademe
• I think Verilog is easier to learn

23
What is HDL?

• HDL Hardware Description Language
• A text-based method for describing hardware to a
  synthesis tool

24
HDL Advantages Over Schematic Entry

• Produce correct designs in less time
• Produce larger and more complex systems per unit
  time
• Shifts focus to specifying functionality
• Synthesis tools automate details of connecting
  gates and devices

25
Design Flow Comparison
Schematic
Text
Netlist
HDL Sim
Gate-Level Simulation
HardwareSynthesis
Implement
Netlist
Implement
26
Key Advantages of HDL-Based Design Methodology

• Operate at higher level of abstraction
• Can debug earlier (behavioral simulator)
• Parameterized design, easy to make wholesale
  modifications to a design (e.g., bus width)

27
Key Advantages of HDL-Based Design Methodology

• Can quickly specify desired behavior
• Example Up-counter with reset

if (reset 1) count lt 0 else count lt count
1
28
Key Advantages of HDL-Based Design Methodology

• Can easily target multiple devices (eases product
  migration)

HDL
FPGA
ASIC
29
Key Advantages of HDL-Based Design Methodology

• HDL is more universal than schematic tools
• Promotes design reuse
• Promotes integration of third party designs, or
  IP (intellectual property)

30
What HDL is NOT

• HDL is not a programming language(HDL is a
  description language)
• HDL is not highly abstract, e.g., implement the
  DSP algorithm y(n) 0.75y(n-1) 0.3x(n)(HDL is
  at the RTL level (register transfer))

31
Synthesizable Subset

• Verilog (and VHDL) began life as simulation and
  modeling tools
• Hardware synthesis developed during the 1990s
• Need to use a subset of Verilog and specific
  coding styles to allow synthesis tool to infer
  correct (and realizable) hardware

32
Synthesizable Subset
Use this to writetestbenches for behavioral
simulation
Verilog
SynthesizableVerilog
Use this to make hardwarein FPGA
33
Most Likely Learning Hurdle

• May try to write HDL code as if it will
  eventually be executed by some mysterious
  processor device in the FPGA
• Code is written sequentially (like a program),
  but you are simply writing descriptions of the
  various hardware entities in your system

34
Verilog Combinational Circuits
35
A Gradual Introduction

• New concepts in boldface
• Verilog keywords in italic
• Refer to your handout...

36
Do Nothing Circuit

• module Gadget
• endmodule

37
Do Nothing with I/O

• module Gadget (a,b,c)// Port modesinput
  a,boutput c
• endmodule

38
NAND Gate Continuous Assignment

• module Gadget (a,b,c)/ Port modes /input
  a,boutput c// Functionalityassign c (a
  b)
• endmodule

39
Bitwise Operators

• NOT
• AND
• OR
• EXOR

40
NAND Gate Procedural Assignment

• module Gadget (a,b,c)// Port modesinput
  a,boutput c// Registered identifiersreg
  c// Functionalityalways _at_ (a or b) c lt (a
  b)
• endmodule

41
Two Gates

• module Gadget (a,b,c,d)// Port modesinput
  a,boutput coutput d// Registered
  identifiersreg c,d// Functionalityalways _at_
  (a or b) begin c lt (a b) d lt a bend
• endmodule

42
Two-Input MUX

• module Mux2 ( A, // A input B, // B
  input Sel, // Selector Y // Output)// Port
  modesinput A,B,Seloutput Y // Registered
  identifiersreg Y// Functionalityalways _at_ (A
  or B or Sel) if (Sel0) Y lt A else Y lt
  B
• endmodule

43
Relational Operators

• Equal to! Not equallt Less
  thangt Greater thanlt Less than or
  equalgt Greater than or equal AND OR

44
More Operators

• gtgt Shift rightltlt Shift left Add- Subtract
  Multiply/ Divide Modulus

Not likely to synthesize!
45
MUX Again...

• // Functionalityalways _at_ (A or B or Sel) if
  (Sel) Y lt B else Y lt A

46
... and Again!

• // Functionalityalways _at_ (A or B or Sel) Y lt
  (Sel) ? B A

47
4-Input MUX

• module Mux4 ( Data, // Data input Sel, //
  Selector Y // Output)// Port modesinput
  30 Datainput 10 Seloutput Y //
  Registered identifiersreg Y//
  Functionalityalways _at_ (Data or Sel) if (Sel
  0) Y lt Data0 else if (Sel 1) Y lt
  Data1 else if (Sel 2) Y lt
  Data2 else Y lt Data3endmodule

48
4-Input MUX Using case

• // Functionalityalways _at_ (Data or Sel) case
  (Sel) 0 Y lt Data0 1 Y lt Data1 2 Y
  lt Data2 3 Y lt Data3 default Y lt
  Data0 endcase

49
Custom MUX

• module Mux16 ( Data, // Data input Sel, //
  Selector Y // Output)// Port modesinput
  150 Datainput 30 Seloutput Y //
  Registered identifiersreg Y//
  Functionalityalways _at_ (Data or Sel) casez
  (Sel) 4b0000 Y lt Data0 4b0001 Y lt
  Data1
• 4b01?? Y lt Data2 default Y lt
  Data3 endcaseendmodule

50
Code Translator (Truth Table)

• module Code_Translator ( Code_In, Code_Out,
  )// Port modesinput 20 Code_Inoutput
  20 Code_Out // Registered identifiersreg
  20 Code_Out// Functionalityalways _at_
  (Code_In) case (Code_In) 3b000 Code_Out lt
  3b101 3b001 Code_Out lt 3b111 3b010
  Code_Out lt 3b001 3b011 Code_Out lt
  3b000 3b100 Code_Out lt 3b100 3b101
  Code_Out lt 3b010 3b110 Code_Out lt
  3b110 3b111 Code_Out lt 3b011
  endcaseendmodule

51
Miscellaneous Techniques

• a,b Data1312,a,b,Data11016a
  assign Y (en) ? X 1bz

52
4-Bit Magnitude Comparator

• module Compare4 ( A, // Data input A B, // Data
  input B AltB, // A is less than B AeqB, // A is
  equal to B AgtB // A is gt than B)// Port
  modesinput 30 A,Boutput AltB,AeqB,AgtB//
  Registered identifiersreg AltB,AeqB,AgtB//
  Functionalityalways _at_ (A or B) begin AltB lt (A
  lt B) AeqB lt (A B) AgtB lt (A gt B)end
• endmodule

53
Parameterized Design

• module Compare4 ( A, // Data input A B, // Data
  input B AltB, // A is less than B AeqB, // A is
  equal to B AgtB // A is gt than B)// Define
  bus widthparameter BusWidth 8// Port
  modesinput BusWidth-10 A,B
• ...
• ...

54
Parameterized Design (Using Compiler Directive)

• define BusWidth 8

55
Lab Projects I
56
Simulating Your Design

• See beginning of From Concept to Working FPGA
  Chip Step-by-Step Instructions
• Demo
• Verilog Boilerplate Generator
• Silos 2001 Behavioral Simulator

57
Combinational Design Projects

• Pick several of the following designs
• 3-to-8 decoder with output enable
• 8-to-3 priority encoder
• 16-bit three-input adder
• 10-bit barrel shifter
• Enter your design and verify in Silos

58
Verilog Sequential Circuits
59
A Gradual Introduction

• New concepts in boldface
• Verilog keywords in italics
• Refer to your handout...

60
D Flip-Flop

• module D_FF (D,Clock,Q)/ Port modes /input
  D,Clockoutput Q// Registered identifiersreg
  Q// Functionalityalways _at_ (posedge Clock) Q
  lt Dendmodule

61
T Flip-Flop, Falling Edge

• module T_FF (T,Clock,Q)/ Port modes /input
  T,Clockoutput Q,// Registered
  identifiersreg Q// Functionalityalways _at_
  (negedge Clock) if (T 1) Q lt
  Qendmodule

62
T Flip-Flop, Dual Outputs

• module T_FF (T,Clock,Q,_Q)/ Port modes
  /input T,Clockoutput Q,_Q// Registered
  identifiersreg Q// Functionalityalways _at_
  (negedge Clock) if (T 1) Q lt Qassign
  _Q Qendmodule

63
Flip-Flop with Async. Reset

• module D_FF (D,Clock,Q,_Q,Reset)/ Port modes
  /input D,Clock,Resetoutput Q,_Q//
  Registered identifiersreg Q//
  Functionalityalways _at_ (negedge Clock or
  posedge Reset) if (Reset 1) Q lt
  0 else Q lt Dassign _Q Qendmodule

64
Flip-Flop with Async. Preset

• module D_FF (D,Clock,Q,_Preset)/ Port modes
  /input D,Clock,_Presetoutput Q//
  Registered identifiersreg Q//
  Functionalityalways _at_ (posedge Clock or
  negedge _Preset) if (_Preset 0) Q lt
  1 else Q lt Dendmodule

65
Flip-Flop, Synchronous Reset

• module D_FF (D,Clock,Q,Reset)/ Port modes
  /input D,Clock,Resetoutput Q// Registered
  identifiersreg Q// Functionalityalways _at_
  (posedge Clock) Q lt (Reset)? 0 Dendmodule

66
A Brief Sermon...

• NOTE Avoid the temptation to design arbitrary
  flip-flop behavior, e.g., ability to trigger on
  both edges of the clock, ability to trigger on
  multiple clock signals, etc. The hardware
  synthesis tool does not magically create new
  hardware from thin air! You have to write circuit
  descriptions that are realizable, that is, can be
  mapped onto existing (known) hardware elements
  such as standard D flip-flops.
• Bottom line Use the constructs listed above
  exactly as shown... dont invent your own!!

67
Data Register

• module Reg16 (D,Clock,Q,Reset)/ Port modes
  /input 150 Dinput Clock,Resetoutput
  150 Q// Registered identifiersreg 150
  Q// Functionalityalways _at_ (posedge Clock or
  posedge Reset) if (Reset 1) Q lt
  0 else Q lt D endmodule

68
Up Counter with Async. Reset

• module CountUp (Clock,Reset,Q)// Port modes
  input Clock,Resetoutput 70 Q// Registered
  identifiersreg 70 Q// Functionalityalways
  _at_ (posedge Clock or posedge Reset) if (Reset
  1) Q lt 0 else Q lt Q 1 endmodule

69
Up Counter with Enable

• // Functionalityalways _at_ (posedge Clock or
  posedge Reset) if (Reset 1) Q lt
  0 else Q lt (Enable) ? Q 1 Q

70
Down Counter

• module CountDown (Clock,Reset,Enable,Init,Q)//
  Port modesinput Clock,Reset,Enable,Initoutput
  70 Q// Registered identifiersreg 70
  Q// Functionalityalways _at_ (posedge Clock or
  posedge Reset) if (Reset 1) Q lt
  0 else if (Init) Q lt 8hFF else if
  (Enable) Q lt Q 1endmodule

71
Loadable Shift Register

• module Shifter (Clock,Reset,Load,D,Q)// Port
  modesinput Clock,Reset,Loadinput 70
  Doutput 70 Q// Registered identifiersreg
  70 Q// Functionalityalways _at_ (posedge
  Clock or posedge Reset) if (Reset 1) Q
  lt 0 else Q lt (Load) ? D
  1b0,Q71endmodule

72
Clock Divider

• parameter MaxCount 12
•  
• always _at_ (posedge Clock or posedge Reset)
• if (Reset) begin
• ClockDiv lt 0
• SlowClock lt 0
• end
• else if (ClockDiv MaxCount)
• begin
• SlowClock lt 1
• ClockDiv lt 0
• end
• else begin
• SlowClock lt 0
• ClockDiv lt ClockDiv1
• end

73
Design Rules

• Generally speaking, follow good design practice
  for digital systems, e.g., avoid gated clocks
• In particular, strive to write descriptions that
  make all flip-flop clocks connect to the master
  clock
• Use asynchronous reset on all flip-flops

74
Design Rules (contd)

• Use a systematic naming convention for
  identifiers
• iIdentifier Module input
• oIdentifier Module output
• rIdentifier Registered
• pIdentifier Parameter
• wIdentifier Wire

75
Topics for Future Exploration

• Finite State Machines
• One-hot encoding
• casez (efficient next-state decoder)
• Data path / controller architecture
• Detailed design rules for FPGAs
• Timing and performance tuning
• Instantiation, multi-module systems
• Testbench design

76
References

• http//www.rose-hulman.edu/doering/fpga_workshop/
  references.htm

77
Lab Projects II
78
Development Procedure

• Introduction to the XS-40 board
• Review the step-by-step development procedure

79
First Design Project

• Implement the following system

SimpleSystem
A
B
(use Pin 19)
(use Pin 44)
C
(use Pin 25)
B A, C A
80
Lab Projects III
81
10-Second Count Down Timer

• Design and implement a 10 second counter (9 down
  to 0) with pause and reset inputs
• Display the count value on the 7-segment display
• Use the 100 MHz on-board clock
• Use the lower two bits of the PC parallel port
  for the pause and reset input signals

82
FPGA System Design withVerilog

• A Workshop Prepared for Rose-Hulman Ventures
• Ed Doering