CAD Techniques for IP-Based and System-On-Chip Designs

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CAD Techniques for IP-Based and System-On-Chip
Designs

• Allen C.-H. Wu
• Department of Computer Science
• Tsing Hua University
• Hsinchu, Taiwan, R.O.C
• Email chunghaw_at_cs.nthu.edu.tw

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Outline

• Introduction
• Basic synthesis tasks
• Codesign of embedded systems
• FPGA synthesis and rapid prototyping
• IP-reuse design methodologies
• System-on-chip design methodologies
• HDL-based layout synthesis methodologies

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Computer-Aided Design (CAD)

• Why?
• What?
• How?

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Human-Centric Design Methodologies

• Designers are the creator of designs.
• Designers are artists.
• Designers pursuit the state of arts.
• Free styles with less discipline.
• May not be efficient on handling complex designs.
• May not be effective on shortening the design
  cycle.

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Human Vs. Computer (Automation)

• Human is good at innovating creation.
• Human is not good at handling tedious and
  repetitive tasks.
• Computer is good at handling tedious and
  repetitive tasks, at least it will never complain
  about it.

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Why needs CAD?

• Design is getting more and more complex.
• Try to develop an error-prone design?
• Time-to-market pressure.

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What is CAD?

• CAD Computer-Aided Design.
• CAD will never be in the leading role of a design
  process!!! Just a supporting role.
• Any techniques, methods, solutions which are used
  solve a problem in a design process.

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How to apply CAD?

• Understand the design process.
• Identify the problems which need CAD supports.
• Correctly define the problem and then solve it.

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A Typical System Design Process
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A Typical Chip Design Process
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Silicon Compilation

• Compiler converting a high-level source code to
  a object code.
• Silicon compiler converting a high-level source
  code (system/chip description) to a piece of
  silicon.

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Synthesis

• Synthesis is a process which converts a design
  from one domain to another
• System-level synthesis
• High-level (Behavioral) synthesis
• RTL synthesis
• Logic synthesis
• Layout synthesis
• HDL-based synthesis

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The Y Chart
Behavioral
Structure
System level
CPU,Mem
System spec.
Ckt level
Chip/Board
Transformation (Synthesis)
Physical
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Design Level
Behavioral
Structure
Physical
System Spec. Algorithm RTL spec. Boolean
Eqn. Differential Eqn.
CPU, Mem. Processor ALU, Reg. Etc., Gate,
FFs Transistor
Chip/board Block/chip Macro-cell Std.
Cell Polygon
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Transitions in the Y Chart
Behavioral
Structure
Synthesis
Optimization
Analysis
Refinement
Abstraction
Generation
Extraction
Physical
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System-Level Synthesis

• Inputs Design functionality (e.g., instruction
  of a computer) and a set of design constraints or
  requirements.
• The transition from a system-level specification
  to one or more subsystem descriptions at the
  algorithmic level (a set of communicating
  concurrent processes, together with a behavioral
  description at the algorithmic level for each
  subsystem).

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High-Level Synthesis

• Starting point a behavioral description at the
  algorithmic level, which defines a precise
  procedure for the computational solution of a
  problem. No notion of CLOCK.
• Outputs controller and datapath.
• Time/area tradeoff.

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RTL-Level Synthesis

• Inputs an RTL netlist and a set of design
  constraints.
• Each component in the netlist is described either
  in behavioral, structural, or logic level.
• Controller synthesis the transition from
  controller behavior to structure.
• Module generation.

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Logic-Level Synthesis

• Inputs Boolean functions and FSMs.
• Outputs the blocks of combinational logic and
  storage elements.
• Logic minimization and optimization.
• Technology mapping.

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Physical-Level Synthesis

• Inputs a hierarchical gate-level netlist which
  may contain hard macros and flexible soft macros.
• Outputs a layout.
• Floorplanning.
• Placement.
• Routing.
• Compaction.

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HDL-Based Synthesis

• Why? What? How?
• VHDL and Verilog originally a simulation-based
  language.
• Programming languages gt hardware!
• Syntax and semantics gaps.
• Compilation is the key to the HDL-based
  synthesis.

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Other Design Issues

• Design entry.
• Design verification and validation
  - simulation
  - formal method
  -
  logic emulation
  - rapid prototyping
  - design rule
  checking
• Testing

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Basic Synthesis Tasks
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The Specification Language Problem

• Many Hardware Descriptive Languages (HDLs) VHDL,
  Verilog, AHPL, ISP, PMS which are derived from
  general programming languages, e.g., ADA, ALGOL,
  C, and PASCAL.
• All general programming languages can be used for
  system-level simulation at behavioral-level.
• No single language can cover the software and
  hardware spectrum!!!!
• CASE problem!!!

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Behavioral Transformations

• Optimizing transformations
  - Procedure in-line expansion
  - Loop unrolling
  - SELECT (IF
  CASE) transformations
• Processes concurrent execution.
• Interprocess communication synchronization
  issues
• Similar to OS problem!

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Communications

• Mapping the logical communication structure onto
  a physical communication structure.
• Synthesis of communication protocols.

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System-Level Partitioning

• Hardware-software codesign.
• A lot of academia studies in this area!!!
• The key to the success is an accurate estimation
  engine to support the partitioning procedure!!!

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Design Exploration

• Time/area tradeoff.
• Architectural-level exploration.
• Memory hierarchy and organization.
• System-level early design planning.
• Design estimation issues.

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The Classical High-Level Synthesis Tasks

• Design representation issues.
• Behavioral transformations.
• Allocations.
• Scheduling.
• Binding.
• Estimation and design exploration.
• Why after a decade of intensive research effort
  high-level synthesis has not yet been accepted by
  industry????