Introduction to FPGA Tools

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Introduction to FPGA Tools
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Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be
able to perform an encryption algorithm by
itself, executing 32 rounds..
Specification (Lab Experiments)
VHDL description (Your Source Files)
Library IEEE use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity RC5_core is
port( clock, reset,
encr_decr in std_logic
data_input in std_logic_vector(31 downto 0)
data_output out std_logic_vector(31
downto 0) out_full in
std_logic key_input in
std_logic_vector(31 downto 0)
key_read out std_logic ) end
AES_core
Functional simulation
Synthesis
Post-synthesis simulation
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Design process (2)
Implementation
Timing simulation
Configuration
On chip testing
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Design Process control from Active-HDL
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Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is signal
A1STD_LOGIC signal B1STD_LOGIC signal
Y1STD_LOGIC signal MUX_0, MUX_1, MUX_2, MUX_3
STD_LOGIC begin A1ltA when (NEG_A'0')
else not A B1ltB when (NEG_B'0') else not
B YltY1 when (NEG_Y'0') else not
Y1 MUX_0ltA1 and B1 MUX_1ltA1 or
B1 MUX_2ltA1 xor B1 MUX_3ltA1 xnor
B1 with (L1 L0) select Y1ltMUX_0 when
"00", MUX_1 when "01", MUX_2 when
"10", MUX_3 when others end MLU_DATAFLOW
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Features of synthesis tools

• Interpret RTL code
• Produce synthesized circuit netlist in a standard
  EDIF format
• Give preliminary performance estimates
• Display circuit schematics corresponding to EDIF
  netlist

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Implementation

• After synthesis the entire implementation process
  is performed by FPGA vendor tools

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Translation
Synthesis
Circuit netlist
Timing Constraints
Constraint Editor
Native Constraint File
Electronic Design Interchange Format
EDIF
UCF
NCF
User Constraint File
Translation
Native Generic Database file
NGD
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Sample UCF File

• NET "clock" LOC "P8"
• NET "controllt0gt" LOC "K4"
• NET "controllt1gt" LOC "K3"
• NET "controllt2gt" LOC "K2"
• NET "reset" LOC "E11"
• NET "segmentslt0gt" LOC "R10"
• NET "segmentslt1gt" LOC "P10"
• NET "segmentslt2gt" LOC "M11"
• NET "segmentslt3gt" LOC "M6"
• NET "segmentslt4gt" LOC "N6"
• NET "segmentslt5gt" LOC "T7"
• NET "segmentslt6gt" LOC "R7"

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Pin Assignment
FPGA
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Constraints Editor
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Circuit netlist
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Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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Placing
FPGA
CLB SLICES
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Routing
FPGA
Programmable Connections
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Configuration

• Once a design is implemented, you must create a
  file that the FPGA can understand
• This file is called a bit stream a BIT file
  (.bit extension)
• The BIT file can be downloaded directly to the
  FPGA, or can be converted into a PROM file which
  stores the programming information

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Report files
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Map report

• Design Summary
• --------------
• Number of errors 0
• Number of warnings 0
• Logic Utilization
• Number of Slice Flip Flops 144 out of
  4,704 3
• Number of 4 input LUTs 173 out of
  4,704 3
• Logic Distribution
• Number of occupied Slices 145 out of
  2,352 6
• Number of Slices containing only related
  logic 145 out of 145 100
• Number of Slices containing unrelated logic
  0 out of 145 0
• See NOTES below for an explanation of
  the effects of unrelated logic
• Total Number 4 input LUTs 210 out of
  4,704 4
• Number used as logic
  173
• Number used as a route-thru
  5
• Number used as 16x1 RAMs 32
• Number of bonded IOBs 74 out of
  176 42
• Number of GCLKs 1 out
  of 4 25
• Number of GCLKIOBs 1 out of
  4 25

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Place route report

• Timing Score 0
• Asterisk () preceding a constraint indicates it
  was not met.
• This may be due to a setup or hold violation.
• --------------------------------------------------
  ------------------------------
• Constraint
  Requested Actual Logic
• 
  Levels
• --------------------------------------------------
  ------------------------------
• TS_clk PERIOD TIMEGRP "clk" 11.765 ns
  11.765ns 11.622ns 13
• HIGH 50
  
• --------------------------------------------------
  ------------------------------
• OFFSET OUT 11.765 ns AFTER COMP "clk"
  11.765ns 11.491ns 1
• --------------------------------------------------
  ------------------------------
• OFFSET IN 11.765 ns BEFORE COMP "clk"
  11.765ns 11.442ns 2
• --------------------------------------------------
  ------------------------------

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Post layout timing report

• Timing summary
• ---------------
• Timing errors 0 Score 0
• Constraints cover 42912 paths, 0 nets, and 1038
  connections
• Design statistics
• Minimum period 11.622ns (Maximum frequency
  86.044MHz)
• Minimum input required time before clock
  11.442ns
• Minimum output required time after clock
  11.491ns

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Timing simulation after implementation
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Timing vs. functional simulation

• Simulation before synthesis is used to verify
  circuit functionality and may differ from the
  one after synthesis and implementation
• Implementation tool generates SDF (Standard
  Delay Format) as a standard delay file and the
  netlist for synthesized VHDL code with delays.
• Generated netlist contains many component
  instantiation statements with library
  references

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SDF file
A part of the SDF file is shown below. It
indicates XOR gate delays (low to high, high to
low) of minimum, typical and worst case timing
( DELAYFILE ( CELL( CELLTYPE XOR)
( INSTANCE U34.Z_VTX)
( DELAY( INCREMENT
( DEVICE 01
(0.3850900.3850900.385090)(0.235177 0.235177
0.235177) )
) ) )
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Netlist from the synthesis tool
U30 MUX21L port map( Z gt n71, A gt n67, B
gt n68, S gt n69) U31 EN port map( Z gt
n67, A gt D1, B gt D0) U32 IV port map( Z
gt n68, A gt n67) U33 EOP port map( Z gt
n69, A gt D6, B gt D7) U34 EO3 port map( Z
gt n70, A gt D3, B gt D2, C gt D4) U35 EO
port map( Z gt n72, A gt D5, B gt n70) U36
EOP port map( Z gt XOR8, A gt n72, B gt n71)
U37 FA1A port map( S gt n73, CO gt n76, CI gt
D3, A gt D2, B gt FF) U38 EO3 port map( Z
gt n74, A gt n68, B gt n73, C gt D4) U39
EOP port map( Z gt FF_COMB_OUT, A gt D5, B gt
n74) end structural
library IEEE library TC200G use
IEEE.std_logic_1164.all use TC200G.components.all
entity CONSYN is port( RSTn, CLK, D0, D1,
D2, D3, D4, D5, D6, D7 in std_logic FF_OUT,
COMB_OUT, FF_COMB_OUT out
std_logic) end CONSYN architecture structural
of CONSYN is signal XOR8, FF, n70, n71, n72, n73,
n74, n75, n76, n67, n68, n69 std_logic begin
FF_OUT lt FF COMB_OUT lt XOR8 FF_reg FD2
port map( Q gt FF, QN gt n75, D gt
XOR8, CP gt CLK, CD gt RSTn)
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Static Timing Analysis
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Static Timing Analyzer

• Performs static analysis of the circuit
  performance
• Reports critical paths with all sources of delays
• Determines maximum clock frequency

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Static Timing Analysis

• Critical Path The Longest Path From Outputs of
  Registers to Inputs of Registers

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Static Timing Analysis

• Min. Clock Period Length of The Critical Path
• Max. Clock Frequency 1 / Min. Clock Period

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Timing Characteristics of Combinational Circuits

• Combinational Circuits Are Characterized by
  Propagation Delays
• through logic components (gates, LUTs)
• through interconnects (routing delays)

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Timing Characteristics of Combinational Circuits
(2)

• Total Propagation Delay of Logic Depends on the
  Number of Logic Levels and Delays of Logic
  Components
• Number of logic levels is the number of logic
  components (gates, LUTs) the signal propagates
  through
• Routing Delays Depend on
• Length of interconnects
• Fanout

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Timing Characteristics of Combinational Circuits
(3)

• Fanout Number of Inputs Connected to One Output
• Each inputs has its capacitance
• Fast switching of outputs with high fanout
  requires higher currents and strong drivers

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Timing Characteristics of Combinational Circuits
(4)

• In Current Technologies Routing Delays Make
  50-70 of the Total Propagation Delays

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XESS Board
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External Connections to XSA Board
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Arrangement of Components
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XSA Board Connectivity
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100 MHz Programmable Oscillator
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Resources Required Reading
Spartan FPGA devices

• Xilinx Spartan-3 FPGA Family
• Complete Data Sheets
• Module 1 Introduction Ordering Information
• Module 2 Functional Description

FPGA Tools
Integrated Interfaces Active-HDL with
Synplify Integrated Synthesis and Implementation
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Hands-on Session

• Enough Talking Lets Get To It!!Brace
  Yourselves!!

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Questions?