FPGA Structure, Programming Principals and Applications: Part II

1
FPGA Structure, Programming Principals and
ApplicationsPart II

• Wu, Jinyuan
• Fermilab
• IEEE Real Time Conference Short Course
• May, 2009

2
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

3
Flashing LED, The First Thing First
Counter
Q23..0

• At least design an LED for an FPGA.
• When a board is first powered up, first test the
  LED flashing function.
• Many things have to be right so that the LED
  flashes
• Power pins must be all connected.
• Configuration devices must be in correct mode.
• Design software must be correct.

4
LED Brightness Variation
FP
Counter
A
Q23..0
AltB

• The LED brightness is varied by changing the
  output pulse duty-cycle.
• Comparator input A is the brightness and B is the
  clock cycle count.
• Look-up table can be added to input A for
  different brightness variation curve.

B
LUT
Counter
A
Q23..0
AltB
B
5
LED Brightness Exponential Drop
if (CO1) Q Q - Q/32
S(-)
SET
Q
D

• Narrow pulse are typically stretched for LED
  display with fix brightness.
• The circuit here provides gradually dim of the
  LED for better visual effect.

FP
A
AltB
Counter
CO
B
Q
Possible Student Lab
6
Exponential Sequence Generator
if (CO1) Q Q - Q/32
S(-)
SET
Q
D

• An exponential sequence is generated using an
  accumulator shown above.
• Note that not even one multiplier is used.
• Other function sequences sine, co-sine, tangent,
  co-tangent etc. can also be generated similarly.

7
Duty-Cycle Based Single-Pin DAC (1)

• The duty-cycle or pulse width of the comparator
  output is proportional to the DAC input at port
  A.
• Use external RC as low-pass filter.
• Output voltage of an ideal LP filter is
  proportional to the DAC input.

8
Duty-Cycle Based Single-Pin DAC (2)
Possible Student Lab

• Use carry-out of the accumulator as the output.
• The number of pulses is proportional to the DAC
  input.
• Rounding error is carried to later cycles.
• Output is smoother.

9
The Frequency Spectrum of DAC (2)

• The first harmonic may be suppressed.
• Works better with regular low-pass filters.

10
The Frequency Spectrum of DAC (1)

• The first harmonic has dominate concentration.
• Works better with notch filter.

11
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

12
Start, Count A Single Layer Loop
The ST signal start the sequence
Counting is enabled
Counting stops
13
A Double-Layer Single-Layer Sequencer
BA AA AA AA AA AA AA AA
0 0 1 2 3 4 255
1 0 1 2 3 4 255
2 0 1 2 3 4 255
3 0 1 2 3 4 255
4 0 1 2 3 4 255

255 0 1 2 3 4 255
0 0 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
1 0 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
2 0 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
3 1 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
4 2 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
255 253 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
0 254 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
0 255 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
0 0 A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop. A double-layer loop is followed by a single-layer loop.
State Control
Outer Loop
Inner Loop
14
An Array Adder
15
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

16
Cares Must Be Taken Outside FPGA (1)
Band Limiting
Band Limiting
FPGA
DAC
ADC
Nyquist Frequency lt (1/2) Sampling Frequency
17
The Trend vs. The Sampling Theorem
There will be no hardware analog processing.
Everything is done digitally in software.
A shaper/low-pass filter is a minimum requirement.
It sounds very stylish ?
18
Cares Must Be Taken Outside FPGA (2)
Dither
FPGA
DAC
ADC
Resolution finer than the ADC LSB can be achieved
by adding noise at ADC input and digital
filtering.
19
Adding Noise for Finer Resolution

• Mechanical pressure gauges usually do not track
  small pressure changes well.
• The gauge readers may lightly tap the gauges to
  get more accurate reading.
• The idea of dithering at ADC input is similar.

Photo Credit www.telegraph.co.uk, trinities.org
20
Some Notes on Philosophy
Wideband Low Noise
Good
Bad
Narrowband Noisy

• Something good in one condition can be bad in
  another condition.
• And vise versa.

21
Why Band Limiting Dithering are Ignored?

• Pre-amplifiers usually have a naturally limited
  bandwidth and an intrinsic noise larger than the
  LSB of the ADC.
• So a lot of time, band limiting and dithering can
  be safely ignored since they are satisfied
  automatically.
• High bandwidth, low noise devices now become
  easily accessible.? A design can be too fast and
  too quiet.?
• Do not forget to review the band limiting and
  dithering requirements for each design.

22
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

23
Data Reduction on Liquid Argon TPC Data
Wire Number
Drift Time
Data from BO detector of FNAL

• Hit waveforms in TPC carry useful information.
• Digitizing the waveforms creates large volume of
  data.
• Data reduction without losing useful information
  is necessary.

24
Slow Variation of Raw Data
U(n1)
A
U(n1)-U(n)
A-B
DFF
B
D
Q

• More than 99 points differ from previous points
  by -1, 0 or 1.
• Huffman Coding can be applied to the differences
  of the data points.

25
The Huffman Coding

• The U(n1)-U(n) value with highest probability is
  assigned to shortest code, i.e., single bit 1.
• Values with lower probabilities are assigned with
  longer codes, e.g., 01, 001, 0001 etc.
• Huffman coded words and regular words are
  distinguished by bit-15.

Regular ADC data for first point or when
U(n1)-U(n) is outside -3
U(n1)-U(n) Code
-4 and others Full 16 bits word
-3 000001
-2 0001
-1 01
0 1
1 001
2 00001
3 0000001
0
0

ADC value (13-bit)
Huffman Coded
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
-1
0
0
0
1
2
Padding or Continue to Next Word
In this example, 6 differences of the data
samples are packed in the 16-bit data word.
26
The Huffman Coding Block
Raw Data
Huffman Coded Data
245 Logic Cells (245/39600)129 0.80
0
0

ADC value (13-bit)
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
-1
0
0
0
1
2

• The block is able to operate at up to 250MHz
  clock in Altera Cyclone III FPGA devices.
• The block uses 245 logic cells, taking 0.6 in an
  EP3C40F484C6 device (129) containing 39600 logic
  cells.

27
The Schematics of the Huffman Coding Block
Difference of Data Points
Huffman Code or Raw Data Selector
Huffman Code Composer
Huffman Code Lookup Table
28
The Compress Ratio of Huffman Coding
N
N/(10.7)

• On typical TPC events a compression ratio of
  about 10 can be achieved.
• Compression ratio is sensitive to high frequency
  noise.

29
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

30
A Mystery of Huffman Coding Ratios on Down
Sampled Data
N
N/(10.7)
(N/5)
(N/5)/(7.5)

• The 5MHz data is down sampled to 1MHz.
• The Huffman Coding compress ratio drops from 10.7
  to 7.5 when the data is down sampled.

31
Averaging in Decimation A Re-discovery
Nyquist Frequency lt (1/2) Sampling Frequency

• Simple down-sampling is not good.
• When the decimation factor is D, an averaging
  over D samples is good either.
• An averaging over 2D samples is necessary.
• There is still aliasing with averaging over 2D
  samples but it is less severe than averaging over
  D samples.

32
Weighted Average, The CIC-2 Filter

• Filter performance can be further improved with
  weighted average over 4D samples.
• The filter is called Cascade-Integrate-Comb
  filter of order 2 (CIC-2).
• The CIC-1 filter is the moving average.

33
Huffman Coding Ratios for 5MHz to 1MHz

• The Huffman Coding compress ratio improves as the
  filter in Dynamic Decimation improves.

34
Dynamic Decimation (DD)

• Only small time intervals, i.e., region of
  interest (ROI) must be sampled at high rate.
• Most time intervals can be sampled with lower
  rate, without losing useful information.

35
A Mystery of Dynamic Decimation Huffman Coding
N
N/10.6
Dynamic Decimation
N/60
N
Dynamic Decimation
Huffman Coding
N
N/10.7
Huffman Coding

• Dynamic Decimation reduces number of samples by
  factor of 10.
• Huffman Coding reduces number of bits from raw
  data by factor of 10.
• When cascaded, the combination reduces number of
  bits by factor of 60.

36
Huffman Coding Ratios for Dynamic Decimation

• The Huffman Coding compress ratio improves as the
  filter in Dynamic Decimation improves.

37
Any Differences ?
Raw
With Dynamic Decimation
38
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

39
TDC Using FPGA Logic Chain Delay

• This scheme uses current FPGA technology ?
• Low cost chip family can be used. (e.g.
  EP2C8T144C6 31.68) ?
• Fine TDC precision can be implemented in slow
  devices (e.g., 20 ps in a 400 MHz chip). ?

IN
CLK
40
Two Major Issues In a Free Operating FPGA

1. Widths of bins are different and varies with
   supply voltage and temperature.
2. Some bins are ultra-wide due to LAB boundary
   crossing

41
Digital Calibration Using Twice-Recording Method
IN

• Use longer delay line.
• Some signals may be registered twice at two
  consecutive clock edges.

N2-N1(1/f)/Dt

• The two measurements can be used
• to calibrate the delay.
• to reduce digitization errors.

CLK
1/f Clock Period Dt Average Bin Width
42
Digital Calibration Result

• Power supply voltage changes from 2.5 V to 1.8 V,
  (about the same as 100 oC to 0 oC).
• Delay speed changes by 30.
• The difference of the two TDC numbers reflects
  delay speed.

N2

• Warning the calibration is based on average bin
  width, not bin-by-bin widths.

N1
Corrected Time
43
Auto Calibration Using Histogram Method

• It provides a bin-by-bin calibration at certain
  temperature.
• It is a turn-key solution (bin in, ps out)
• It is semi-continuous (auto update LUT every 16K
  events)

16K Events
DNL Histogram
S
LUT
In (bin)
Out (ps)
44
Good, However

• Auto calibration solved some problems ?
• However, it wont eliminate the ultra-wide bins ?

45
Cell Delay-Based TDC Wave Union Launcher

• The wave union launcher creates multiple logic
  transitions after receiving a input logic step.
• The wave union launchers can be classified into
  two types
• Finite Step Response (FSR)
• Infinite Step Response (ISR)
• This is similar as filter or other linear system
  classifications
• Finite Impulse Response (FIR)
• Infinite Impulse Response (IIR)

Wave Union Launcher
In
CLK
46
Wave Union Launcher A (FSR Type)
1 Unleash
0 Hold
Wave Union Launcher A
In
CLK
47
Wave Union Launcher A 2 Measurements/hit
1 Unleash
48
Sub-dividing Ultra-wide Bins
1 Unleash

• Device EP2C8T144C6
• Plain TDC
• Max. bin width 160 ps.
• Average bin width 60 ps.
• Wave Union TDC A
• Max. bin width 65 ps.
• Average bin width 30 ps.

1
2
49
Measurement Result for Wave Union TDC A

• Plain TDC
• delta t RMS width 40 ps.
• 25 ps single hit.
• Wave Union TDC A
• delta t RMS width 25 ps.
• 17 ps single hit.

Raw
TDC LUT
Histogram
53 MHz Separate Crystal
Wave Union
Histogram
50
More Measurements

• Two measurements are better than one.
• Lets try 16 measurements?

51
Wave Union Launcher B (ISR Type)
Wave Union Launcher B
1 Oscillate
0 Hold
In
CLK
52
Wave Union Launcher B 16 Measurements/hit
1 Hit 16 Measurements _at_ 400 MHz
53
Delay Correction

• The raw data contains
• U-Type Jumps 48-63?16-31
• V-Type Jumps other small jumps.
• W-Type Jumps 16-31?48-63

• Delay Correction Process
• Raw hits TN(m) in bins are first calibrated into
  TM(m) in picoseconds.
• Jumps are compensated for in FPGA so that TM(m)
  become T0(m) which have a same value for each
  hit.
• Take average of T0(m) to get better resolution.

The processes are all done in FPGA.
54
The Test Module
Data Output via Ethernet
FPGA with 8ch TDC
Two NIM inputs
BNC Adapter to add delay _at_ 150ps step.
55
Test ResultNIM Inputs
RMS 10ps
140ps
0
1
2
Wave Union TDC B
Wave Union TDC B
BNC adapters to add delays _at_ 140ps step.

NIM/ LVDS
Wave Union TDC B
Wave Union TDC B
-
LeCroy 429A NIM Fan-out
Wave Union TDC B
NIM/ LVDS
Wave Union TDC B

Wave Union TDC B
Wave Union TDC B
56
Multi-Sampling TDC FPGA
Clock Domain Changing
Multiple Sampling
Q3
QF
c0
c0
Q2
QE

• Ultra low-cost 48 channels in 18.27
  EP2C5Q208C7.
• Sampling rate 360 MHz x4 phases 1.44 GHz.
• LSB 0.69 ns.

c90
Q1
QD
c180
Q0
c90
c270
DV
T0 T1
Trans. Detection Encode
4Ch
Coarse Time Counter
TS
Logic elements with non-critical timing are
freely placed by the fitter of the compiler.
This picture represent a placement in Cyclone FPGA
57
Issues of Coarse Time Counter
000 001 011 010 110 111 101 100
Coarse Time Counter
Coarse Time Counter
Gray Code Counter
Coarse Time Counter

• There are some common misunderstandings on coarse
  time counters in a TDC
• Tow coarse time counters are needed, driven by
  clocks with 180 degree phase difference.
• The coarse time counter should be a Gray code
  counter.
• Dual counters and/or Gray code counters are only
  needed in one ASIC TDC architecture.
• In the architectures used by FPGA TDC and some
  ASIC TDC, only one plain binary counter is needed
  as coarse time counter.

58
Delay Line Based TDC Architectures
Delay Hit Delay CLK Delay Both
CLK is used as clock
HIT is used as clock
Only this architecture needs dual coarse time
counters.
59
Implementation of Coarse Time Counter
Coarse Time Counter
Coarse Time
In
Fine Time Encoder
Fine Time
ENA
CLK
Hit Detect Logic
Data Ready
60
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

61
Classical Picture of Serial Communications
Parallel -to-Serial Converter
FIFO
Serial-to -Parallel Converter
Local Logic
PLL
X1
X2
Recovered Clock

• The parallel data is converted to serial bits
  driven by crystal oscillator X1 in the
  transmitter device.
• The serial data stream is used to generate a
  recovered clock at the receiver device with a
  phase lock loop (PLL).
• The recovered clock is used to drive the
  serial-to-parallel converter and store the data
  into a first-in-first-out (FIFO) buffer.
• The FIFO buffer is used to transfer data from the
  recovered clock domain to the local clock domain
  generated by crystal oscillator X2.

62
Serial Data Receiving Without PLL etc.
Digital Serial-to -Parallel Converter
Parallel -to-Serial Converter
Local Logic
X1
X2

• Generating recovered clock with PLL, VCO, VCXO
  etc. is an analog process and it is not
  convenient to generate in an FPGA, especially for
  applications with multiple receiving channels.
• There are pure digital methods to receive the
  serial data.
• Digital Phase Follower 1bit/CLK
• The Two-Cycle Serial IO 1bit/(2CLK)
• FM Encoder and Decoder 1bit/(2-16CLK)
• Clock-Command Combined Carrier Coding (C5)
  4bits/(20CLK)
• The transmitter and receiver can be driven by two
  independent free running crystal oscillators.

63
Digital Phase Follower

• The input data rate is 1bit/clock cycle.
• Four clock phases, c0, c90, c180 and c270 are
  used to detect input transition edge.
• The phase for data sample follows the variation
  of the transition edge.

64
Schematics of Digital Phase Follower

• CLK 375MHz
• Data Rate 375Mbits/s

65
The Two-Cycle Serial IO
One data bit is transmitted every 2 clock cycles.
Transmitter
CLK1
Data Out
Input data are stable at these clock edges.
Receiver
CLK2
Data In
A logic transition is detected between these two
falling edges.

• This scheme is slower than digital phase follower
  but the logic is simpler.
• The CLK1 and CLK2 can be generated with two free
  running crystal oscillators.

66
Schematics of the Two-Cycle Serial IO

• CLK 200MHz
• Data Rate 100Mbits/s

67
The FM coding
0
start bit 1
0
0
1
1

• A bit is transmitted in two unit time intervals,
  usually in two internal clock cycles at frequency
  f.
• For bit1, the output toggles each cycle, i.e.,
  with frequency (f/2) and for bit0, the output
  toggles every two cycles, i.e., with frequency
  (f/4).
• When not transmitting data, the output toggles at
  frequency (f/4), until seeing the start bit.
• The data stream is naturally DC balanced suitable
  for AC coupled transmission.
• The polarity of the interconnection doesnt
  matter.

68
Schematics of FM Decoder

• CLK 212MHz
• Data Rate 26.5Mbits/s
• The ratio 8 CLK cycles/bit in this design is not
  an intrinsic limit.

69
The Clock-Command Combined Carrier Coding (C5)

• A data train contains 5 pulses and each pulse is
  transmitted in four unit time intervals, usually
  in four internal clock cycles at frequency f.
• Information is carried with wide, normal and
  narrow pulses and the first pulse is always wide
  or narrow.
• When not transmitting data, all pulses have
  normal width.
• The data stream is DC balanced over 5 pulses
  suitable for AC coupled transmission.
• All leading edges are evenly spread so that the
  pulse train can be used directly drive the
  receiver side logic or PLL.

70
Schematics of C5 Decoder

• Data Rate 36ns/bit or 27.7Mbits/s
• Internal clock 111MHz

71
Outline

• Counting
• Example LED brightness and DAC
• Simple Sequencing
• Bandwidth and Noise Issues
• General Remarks on Sampling Theorem and
  Dithering.
• Example Huffman Coding
• Example Decimation Dynamic Decimation
• After-fact Calibration
• Several Topics on FPGA Based TDC
• Serial Communication with Independent Crystals
• Minimum Synchronization

72
Fixed Latency Everywhere?
Front End
Front End
Front End
Front End
Front End
Front End
Timing Reference
SER
SER
SER
?
Trigger
Trigger
DESER
DESER
DESER

• In classical trigger system, all cables must have
  fixed propagation delay.
• Serial links intrinsically do not have fixed
  latency.
• Do we need fixed latency at all?
• No.

73
Hit Time Coding and Transmitting
CLKCMD
Hit

• Hits in each channel are coded as bits
  representing small time intervals.
• Bit patterns are merged in a front-end module.

74
Cable Delay Self Timing
Detector Processing Board

• At system initialization, all the Detector
  Processing Boards send out a special word in the
  same clock cycle as start mark.
• At the receiving end, the absolute arrival time
  from each board can be unknown and different.
  However, the start mark is recognized and stored
  in the addresses 0 of the corresponding receiving
  buffer. The words after the start mark are
  stored in sequence.

Detector Processing Board
Detector Processing Board
Processing Support Board
75
An Example
76
Hit Merging and Coincidence
Processing Support Board
Coincidence Module
Processing Support Board

• Hits from different inputs in the Processing
  Support Board are merged together with an OR
  function and sent out as a serial data stream.
• The Coincidence Module re-align the different
  stream in the receiver buffers.
• Inside the Coincidence Module, the coincidence is
  searched as AND functions of the hit streams from
  opposite detector sectors. Very likely, a
  boundary coverage logic is applied, e.g.
• Trigger TN HAN(HBN HCN).
• The boundary coverage for time domain is also
  necessary. This is satisfied by checking
  adjacent bits in the buffered words, e.g.
• Trigger TN (HAN1 HAN
  HAN-1)(HBN HCN).

77
Post-Scripts

• Some Extra Words for the
• Young Old

78
About FPGA Myths Thinking

• We commonly heard about FPGA
• FPGA is cheap.
• FPGA is fast.
• FPGA is large.
• FPGA can do anything.
• Not really.
• At least it is not always the case.
• Good design tricks are needed in order to take
  full advantages of FPGA devices and to avoid
  drawbacks of FPGA devices.

• FPGA 16-1500, Micro-Processor 100-500.
• FPGA 500MHz, Micro-Processor 1-3GHz.
• FPGA logic consumes more transistors.
• Only if the information is collected in FPGA.

79
Moores Law
Taken from www.intel.com

• Number of transistors in a package
• x2 /18months

80
Status of Moores Law an Inconvenient Truth
Taken from www.intel.com

• of transistors
• Yes, via multi-core.
• Clock Speed
• ?

81
Complexity in FPGA Designs

• Excessive Complexity in FPGA Designs
• Fevers of Moores Law Myths No Thinking
• Complexity causes higher FPGA cost.
• Complexity creates indirect costs such as PCB
  layout, assembly, power consumption, cooling etc.
• Complexity confuses people, including designers.

82
Indirect Cost of Complexity
If something like this can do the job
why do these?
83
The Winning Line of FPGA Design
O Freunde, nicht diese Töne!

• We commonly heard
• FPGA devices contains millions gate.
• High parallelism can be implemented in FPGA.
• FPGA cost drops by half every 18 months.
• We want to emphasize, especially to our young
  students
• Creativity,
• Creativity,
• Creativity, on Arithmetic ops, on Algorithms, on
  Architectures on All Aspects.

84
The End

• Thanks