FPGA Design Flow based on Aldec Active-HDL FPGA Board

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FPGA Design Flow based on Aldec Active-HDLFPGA
Board
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FPGA Design Flow
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Design flow (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be
able to perform an encryption algorithm by
itself, executing 32 rounds..
Specification (Lab Experiments)
VHDL description (Your Source Files)
Library IEEE use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity RC5_core is
port( clock, reset,
encr_decr in std_logic
data_input in std_logic_vector(31 downto 0)
data_output out std_logic_vector(31
downto 0) out_full in
std_logic key_input in
std_logic_vector(31 downto 0)
key_read out std_logic ) end
AES_core
Functional simulation
Synthesis
Post-synthesis simulation
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Design flow (2)
Implementation
Timing simulation
Configuration
On chip testing
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Tools used in FPGA Design Flow
Functionally verified VHDL code
Design
VHDL code
Synplicity Synplify Pro
Xilinx XST
Synthesis
Netlist
Implementation
Xilinx ISE
Bitstream
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Synthesis
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Synthesis Tools
Xilinx XST
Synplify Pro

• and others

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Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is signal
A1STD_LOGIC signal B1STD_LOGIC signal
Y1STD_LOGIC signal MUX_0, MUX_1, MUX_2, MUX_3
STD_LOGIC begin A1ltA when (NEG_A'0')
else not A B1ltB when (NEG_B'0') else not
B YltY1 when (NEG_Y'0') else not
Y1 MUX_0ltA1 and B1 MUX_1ltA1 or
B1 MUX_2ltA1 xor B1 MUX_3ltA1 xnor
B1 with (L1 L0) select Y1ltMUX_0 when
"00", MUX_1 when "01", MUX_2 when
"10", MUX_3 when others end MLU_DATAFLOW
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Circuit netlist (RTL view)
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Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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RTL view in Synplify Pro

• General logic structures can be recognized in RTL
  view

incrementer
comparator
MUX
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Crossprobing between RTL view and code

• Each port, net or block can be chosen by mouse
  click from the browser or directly from the RTL
  View

• By double-clicking on the element its source code
  can be seen

• Reverse crossprobing is also possible if section
  of code is marked, appropriate element of RTL
  View is marked too

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Technology View in Synplify Pro

• Technology view is a mapped RTL view. It can be
  seen by pressing button or by
  double-click on .srm file
• As in case of RTL View, buttons
  can be used here
• Two additional buttons are enabled - show
  critical path
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  - open timing analyst

Pay attention technology view is usually large
and presented on number of sheets
Technology view is presented using device
primitives
Ports, nets and blocks browser
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Viewing critical path

• Critical path can be viewed by pressing on
  
• Delay values are written near each component of
  the path

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Timing Analyst

• Timing analyst opened by pressing on
• Timing analyst gives a possibility to analyze
  different paths in the design
• Timing analyst can be opened only from Technology
  View

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Implementation
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Implementation

• After synthesis the entire implementation process
  is performed by FPGA vendor tools

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Translation
Synthesis
Circuit netlist
Timing Constraints
Constraint Editor or Text Editor
Native Constraint File
Electronic Design Interchange Format
EDIF
UCF
NCF
User Constraint File
Translation
Native Generic Database file
NGD
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Pin Assignment
FPGA
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Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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Placing
FPGA
CLB SLICES
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Routing
FPGA
Programmable Connections
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Configuration

• Once a design is implemented, you must create a
  file that the FPGA can understand
• This file is called a bit stream a BIT file
  (.bit extension)
• The BIT file can be downloaded directly to the
  FPGA, or can be converted into a PROM file which
  stores the programming information

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Two main stages of the FPGA Design Flow
Implementation
Synthesis
Technology dependent
Technology independent
RTL Synthesis
Map
Place Route
Configure

• Code analysis
• - Derivation of main logic constructions
• Technology independent optimization
• Creation of RTL View

• Mapping of extracted logic structures to device
  primitives
• Technology dependent optimization
• Application of synthesis constraints
• Netlist generation
• Creation of Technology View

• Placement of generated netlist onto the device
• Choosing best interconnect structure for the
  placed design
• Application of physical constraints

• Bitstream generation
• Burning device

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Static Timing Analysis
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Static Timing Analyzer

• Performs static analysis of the circuit
  performance
• Reports critical paths with all sources of delays
• Determines maximum clock frequency

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Static Timing Analysis

• Critical Path The Longest Path From Outputs of
  Registers to Inputs of Registers

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Static Timing Analysis

• Min. Clock Period Length of The Critical Path
• Max. Clock Frequency 1 / Min. Clock Period

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Timing Characteristics of Combinational Circuits

• Combinational Circuits Are Characterized by
  Propagation Delays
• through logic components (gates, LUTs)
• through interconnects (routing delays)

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Timing Characteristics of Combinational Circuits
(2)

• Total Propagation Delay of Logic Depends on the
  Number of Logic Levels and Delays of Logic
  Components
• Number of logic levels is the number of logic
  components (gates, LUTs) the signal propagates
  through
• Routing Delays Depend on
• Length of interconnects
• Fanout

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Timing Characteristics of Combinational Circuits
(3)

• Fanout Number of Inputs Connected to One Output
• Each inputs has its capacitance
• Fast switching of outputs with high fanout
  requires higher currents and strong drivers

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Timing Characteristics of Combinational Circuits
(4)

• In Current FPGAs Routing Delays
• typically account for 45 to 65 of the
• total path delays

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Timing simulation after implementation
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Timing vs. functional simulation

• Simulation before synthesis is used to verify
  circuit functionality and may differ from the
  one after synthesis and implementation
• Implementation tool generates SDF (Standard
  Delay Format) as a standard delay file and the
  netlist for synthesized VHDL code with delays.
• Generated netlist contains many component
  instantiation statements with library
  references

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SDF file
A part of the SDF file is shown below. It
indicates XOR gate delays (low to high, high to
low) of minimum, typical and worst case timing
( DELAYFILE ( CELL( CELLTYPE XOR)
( INSTANCE U34.Z_VTX)
( DELAY( INCREMENT
( DEVICE 01
(0.3850900.3850900.385090)(0.235177 0.235177
0.235177) )
) ) )
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Netlist from the synthesis tool
U30 MUX21L port map( Z gt n71, A gt n67, B
gt n68, S gt n69) U31 EN port map( Z gt
n67, A gt D1, B gt D0) U32 IV port map( Z
gt n68, A gt n67) U33 EOP port map( Z gt
n69, A gt D6, B gt D7) U34 EO3 port map( Z
gt n70, A gt D3, B gt D2, C gt D4) U35 EO
port map( Z gt n72, A gt D5, B gt n70) U36
EOP port map( Z gt XOR8, A gt n72, B gt n71)
U37 FA1A port map( S gt n73, CO gt n76, CI gt
D3, A gt D2, B gt FF) U38 EO3 port map( Z
gt n74, A gt n68, B gt n73, C gt D4) U39
EOP port map( Z gt FF_COMB_OUT, A gt D5, B gt
n74) end structural
library IEEE library TC200G use
IEEE.std_logic_1164.all use TC200G.components.all
entity CONSYN is port( RSTn, CLK, D0, D1,
D2, D3, D4, D5, D6, D7 in std_logic FF_OUT,
COMB_OUT, FF_COMB_OUT out
std_logic) end CONSYN architecture structural
of CONSYN is signal XOR8, FF, n70, n71, n72, n73,
n74, n75, n76, n67, n68, n69 std_logic begin
FF_OUT lt FF COMB_OUT lt XOR8 FF_reg FD2
port map( Q gt FF, QN gt n75, D gt
XOR8, CP gt CLK, CD gt RSTn)
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Celoxica RC10FPGA Board
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Joystick needs to be debounced(you can use
circuit from experiment 2)
input
DD clock cycles
DD clock cycles
output
DD clock cycles
DD clock cycles
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Piezo Buzzer

• Outputted signals should be 50 duty square
  waves, meaning the signal is high and low for
  equal amounts of time.

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Demo
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Exp.2 Part 2

• Programmable (joystick) timer (counter clock
  divider) with alarm (buzzer).

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Questions?
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Hands-on Session

• Enough Talking Lets Get To It!!Brace
  Yourselves!!