VHDL Controller

1
VHDL Controller

• ECE-445
• Computer Organization
• Dr. Ron Hayne
• Electrical and Computer Engineering

2
Single-Bus Architecture
BUS A
6
6
MAR
6
PC
MEM
MDR
1
2
IR
1
2
6
MUX
MUX
2
Y
1
1
REGS
A
B
ALU
NZVC
R
Z
3
Branch Instructions
BGTZ LOOP

• Execute
• if CCgt0, PC ? PC IR

• Condition Code
• Z 0, N 0

4
Program Counter

• entity CNT6 is
• port( CLK in std_logic
• Enable_In in std_logic
• DATA_IN in std_logic_vector(5 downto
  0)
• Enable_Cnt in std_logic
• Enable_Out in std_logic
• DATA_OUT out std_logic_vector(15
  downto 0))
• end CNT6

5
Counter Architecture

• architecture BEHAVE of CNT6 is
• signal CNT std_logic_vector(5 downto 0)
• (others gt '0')
• begin
• counter process
• begin
• wait until (CLK '1' and not CLK'STABLE)
• if Enable_In '1' then
• CNT lt DATA_IN
• elsif Enable_Cnt '1' then
• CNT lt CNT "000001"
• end if
• end process

6
Counter Process

• output process(Enable_Out, CNT)
• begin
• if Enable_Out '1' then
• DATA_OUT lt "0000000000" CNT
• else
• DATA_OUT lt (others gt 'Z')
• end if
• end process
• end BEHAVE

7
ALU

• entity ALU16 is
• port( OP in std_logic_vector(2 downto 0)
• A in std_logic_vector(15 downto 0)
• B in std_logic_vector(15 downto 0)
• CIN in std_logic
• R out std_logic_vector(15 downto 0)
• N out std_logic
• Z out std_logic
• V out std_logic
• C out std_logic )
• end ALU16

8
Partial VHDL Model

• ADDER for I in 15 downto 0 generate
• SI FA port map ( A gt A(I), B gt B(I),
• CIN gt CARRY(I), S gt
  SUM(I),
• COUT gt CARRY(I 1) )
• end generate
• MUX Mux8to1 port map ( S gt Op,
• I0 gt A,
• I1 gt SUM,
• I2 gt X"0000",
• I3 gt X"0000",
• I4 gt X"0000",
• I5 gt X"0000",
• I6 gt SUM,
• I7 gt B,
• Z gt RESULT )

9
Condition Codes

• R lt RESULT
• N lt RESULT(15)
• V lt ((A(15) and B(15) and not SUM(15)) or
• (not A(15) and not B(15) and SUM(15)))
• Z lt not (RESULT(15) or RESULT(14) or ...
• or RESULT(1) or RESULT(0))
• C lt CARRY(16)

10
Single-Bus Architecture
BUS A
6
6
MAR
6
PC
MEM
MDR
1
2
IR
1
2
6
MUX
MUX
2
Y
1
1
REGS
A
B
ALU
NZVC
R
Z
11
Instruction Encoding
EA Effective Address
12
Instruction Encoding
13
Control Unit Organization
Control Step Counter
CLK
Run
Step DCD
T0
T7
. . .
I0
InstructionDCD
. . .
I7
S0
N
ConditionCodes
SRC_MODEDCD
Encoder
IR
S3
. . .
. . .
C
D0
DST_MODEDCD
D1
. . .
Halt
Reset
Control Signals
14
Decoder

• entity DCD3to8 is
• port( I in std_logic_vector(2 downto 0)
• D out std_logic_vector(7 downto 0))
• end DCD3to8

15
Decoder Architecture

• process(I)
• begin
• case I is
• when "000" gt
• D lt "00000001"
• when "001" gt
• D lt "00000010"
• when "111" gt
• D lt "10000000"
• when others gt
• D lt "00000000"
• end case
• end process

16
Instruction DCD

• signal I std_logic_vector(7 downto 0)
• (others gt '0')
• alias OPCODE std_logic_vector(2 downto 0) is
• IR_OUT2(15 downto 13)
• Instruction_DCD DCD3to8 port map ( I gt
  OPCODE,
• D gt I )

17
Control Unit Organization
Control Step Counter
CLK
Run
Step DCD
T0
T7
. . .
I0
InstructionDCD
. . .
I7
S0
N
ConditionCodes
SRC_MODEDCD
Encoder
IR
S3
. . .
. . .
C
D0
DST_MODEDCD
D1
. . .
Halt
Reset
Control Signals
18
Control Step Counter

• entity CNT3 is
• port( CLK in std_logic
• Clear in std_logic
• Enable_Cnt in std_logic
• COUNT out std_logic_vector(2
  downto 0))
• end CNT3
• NOTE Falling Edge Triggered

19
Counter Architecture

• architecture BEHAVE of CNT3 is
• signal CNT std_logic_vector(2 downto 0)
• (others gt '1')
• begin
• counter process
• begin
• wait until (CLK '0' and not CLK'STABLE)
• if Clear '1' then
• CNT lt "000"
• elsif Enable_Cnt '1' then
• CNT lt CNT "001"
• end if
• end process
• COUNT lt CNT
• end BEHAVE

20
Step CNT

• signal Reset std_logic '0'
• signal Run std_logic '1'
• signal Step std_logic_vector(2 downto 0)
• (others gt '0')
• signal T std_logic_vector(7 downto 0)
• (others gt '0')
• Step_CNT CNT3 port map ( CLK gt CLK,
• Clear gt Reset,
• Enable_CNT gt Run,
• COUNT gt Step
  )
• Step_DCD DCD3to8 port map ( I gt Step,
• D gt T )

21
Control Unit Organization
Control Step Counter
CLK
Run
Step DCD
T0
T7
. . .
I0
InstructionDCD
. . .
I7
S0
N
ConditionCodes
SRC_MODEDCD
Encoder
IR
S3
. . .
. . .
C
D0
DST_MODEDCD
D1
. . .
Halt
Reset
Control Signals
22
Control Signal Logic Functions
23
Encoder

• encoder process(T)
• begin
• PC_Inc lt T(0)
• MAR_En_In lt T(0) or (T(4) and I(0) and S(0)
  and D(1))
• REGS_Read lt T(3) and I(0) and S(0)
• Reset lt (T(4) and I(0) and S(0) and D(0)) or
• (T(5) and I(0) and S(0) and D(1))

24
Questions?