EE360R

1

• EE360R
• Laboratory Exercise 3

2
Overview

• RTL level system design using Verilog (Behavioral
  Modeling)
• Part A Synchronous Serial Port (SSP)
• Part B Integration of SSP with ARM system using
  a SoC bus interface called Wishbone
• Tools
• Simulation VCS, Virsim
• Synthesis Design Vision

3
Overview RTL design with Verilog
Vcs/ virsim

• Verilog
• A hardware description lang.
• Structural description
• Behavioral description
• Synthesizable code

RTL level
lab3
Design Analyzer (Synthesis tool)
Gate level
Virtuoso editor
lab2
SE (APR tool)
Tr. level
lab1
Virtuoso editor
Layout
4
Specifications - SSP

• Block Diagram of SSP

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Specifications - SSP

• Transmit FIFO (TxFIFO), Receive FIFO (RxFIFO)
• 8-bit wide, 4-locations deep FIFO
• Only valid data need to be buffered
• FIFO full generates SSPTXINTR signal
• Transmit and receive logic
• Performs parallel-to-serial and
  serial-to-parallel conversion
• Transfer (or receive) data synchronously

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Specifications - SSP

• Signal Description
• CLEAR_B Low active clear signal
• SSPCLKIN, SSPCLKOUT
• Synchronization clock for data transfer
• 2 times slower than PCLK
• PSEL chip select signal for SSP
• PWRITE 1 Write, 0 Read
• SSPFSSIN, SSPFSSOUT indicates starting of data
  transfer
• SSPOE_B Low active output enable signal,
  indicates when SSPTXD is valid
• Assume perfect synchronization between SSPCLKIN
  and SSPCLKOUT testing is done with external
  loop back

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Specifications SSP Timing Diagram

• Frame format

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Specifications SSP Timing Diagram

• Frame Format (continuous transfer)

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System Overview given system
ARM RISC, 4 stage pipelined, LD/ST
architecture
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System Overview new system
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Specifications - WISHBONE

• Activities need to be supported
• Instruction Read
• When ARM accesses h0000000-h000FFFF
• Generates memory access signals
• Deliver instructions from memory to ARM
• Mem-gtSlave-gtMaster-gtARM
• Data Read
• When ARM accesses h0010001
• Generate SSP access signals
• Deliver data from SSP to ARM
• SSP-gtSlave-gtMaster-gtARM

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Specifications - WISHBONE

• Activities (continued)
• Data Write
• When ARM accesses h0010000
• Generate SSP access signals
• Deliver data from ARM to SSP
• ARM-gtMaster-gtSlave-gtSSP
• Interrupt handling
• Stop ARM by holding phi1 and phi2
• e.g. SSP Full Interrupt
• SSP-gtSlave-gtMaster (holds clocks)

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Integration Tip

• Phi1 and phi2 should be non-overlapping clocks
  (their edges should be non-overlapping).
• Check the functionality and synthesizability of
  your sub-module frequently.
• You can check if your module is synthesizable by
  reading it from Design Analyzer (should have no
  error when read).

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Design
test_module.v

• Procedure
• Design a module (module.v)
• Make a testbench file (test_module.v)
• -gt can be recycled for other modules after
  small modification
• Make a makefile (make_module)
• -gt simple list of verilog files to compile
• Run simulation
• (vcs RI Mupdate f make_module)

provide input data/signals
module.v
Observe output data/signals
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Simulate

• Write your own assembly test program using ARM
  instructions.
• Refer ARM manual given to you.
• Compile the program and save it to
  /images/mem.data (-gt actual memory image)
• asm_arm myprogram gt mem.data
• Template mem.data is given for testing you may
• choose to create your own
• Run VCS/Virsim
• Makefile for TOP module

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Synthesize (new modules only)

• Using Design Vision
• Code should be synthesizable
• (i.e. readable from Design Vision without
  error messages)
• Library has no flops with async reset use
  synchronous reset if you need to clear flop
  contents
• Observe area/timing trade off
• First, run without constraint (initial run)
• -gt you can get initial area and initial
  arrival time
• Run with area optimization option with smaller
  area than initial area
• Run with timing optimization option with smaller
  clock period than initial arrival time