LucasLehmer Primality Tester Presentation 8 March 22nd 2006

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Lucas-Lehmer Primality TesterPresentation
8March 22nd 2006

• Team W-4
• Nathan Stohs W4-1
• Brian Johnson W4-2
• Joe Hurley W4-3
• Marques Johnson W4-4
• Design Manager
• Prateek Goenka

Overall Objective Modular Arithmetic unit with a
creative use
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Status

• Finished
• Project Chosen
• C simulations
• Behavioral Verilog
• Structural Verilog
• Floor Plan
• Schematics
• Pathmill Simulation of Top Level
• In Progress
• Layout
• Layout Simulations
• To Do
• More Layout/Simulations

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Transistor Counts
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Sub_16
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Shift Left
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Mod Add
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Mod Add Schematic
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Mod Add Simulation

• 127 68 Mod 127 69

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Block Area Estimates (Updated)
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Updated Floorplan
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Partial Product Progress
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Overall Status
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Whats Next

• Continue Layout
• Continue Simulating Layout
• Power Estimations on Layout
• Change Design of Registers
• Optimize

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Questions?