Datapath in Operation for an Rtype Instruction

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Datapath in Operation for an R-type Instruction
add t1, t2, t3
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Datapath in Operation for a Load Instruction
lw t1, offset(t2)
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Datapath in Operation for a Store Instruction
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Datapath for beq
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Performance

• Assume that
• Memory access 200ps
• ALU and adders 100 ps
• Register file read 50ps
• Register file write 50ps (the clk-to-q delay)
• PC update 10ps (the clk-to-q delay)
• The setup time of DFFs 10ps
• Other parts do not have delay
• How fast is
• An R-type instruction?
• A lw instruction?
• A sw instruction?
• A beq instruction?
• Need to find the critical path the longest path
  

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R-type

• So, the clock needs to be at least
  102005010010 370ps
• Will there be a problem if the next instruction
  is also an R-type instruction, considering that
  the register is written and stable only after the
  next rising edge of the clock?
• Figure not to the exact scale

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lw

• So, the clock needs to be at least
  102005010020010 570ps
• Figure not to the exact scale

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beq

• So, it is 102005010010 370ps
• Figure not to the exact scale

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Clock cycle

• So, how long should the clock cycle be?
• Is it efficient?