Cpsc 318 Computer Structures Lecture 12 Control Unit

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Cpsc 318Computer Structures Lecture 12
Control Unit

• Dr. Son Vuong
• (vuong_at_cs.ubc.ca)
• March 1-3, 2005

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Outline

• Datapath Walkthroughs
• ALU Design
• Booth Algorithm for Signed Multiplication
• Control Unit (now)
  

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Recap 1/3 Five Components of a Computer
Keyboard, Mouse
Computer
Devices
Memory (passive) (where programs, data live
when running)
Processor
Disk (where programs, data live when not
running)
Input
Control
Output
Datapath
Display, Printer
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Recap 2/3 Datapaths 5 Basic Steps
rd
instruction memory
PC
rs
registers
Data memory
rt
4
imm
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Recap 3/3 Datapath Summary

• Weve seen the datapath based on data transfers
  required to perform instructions
• A controller causes the right transfers to happen

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Single-Cycle Datapath
MUX
Add
Add
ALU
result
ltlt 2
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Reg Write
MemWrite
Instr25-21
read
Data
register 1
read
Memory
read
ALU
MemtoReg
address
data 1
PC
Instr20-16
zero
read
read
ALUSrc
instruction
a
ddress
register 2
ALU
data
31-0
result
read
MUX
data 2
write
write
Instruction
MUX
MUX
register
data
memory
Instr15-11
Memread
RegDest
write
data
32
Sign
16
Instr15-11
ALU
extend
Control
ALUop
Instr5-0
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Multi-cycle Data Path
Instruction and data in same memory unit Add
internal registers (IR and MDR) Single ALU
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Multiple Sources -- Single Sink
2
PC4 instruction fetch rsrt r-type
instructions rssign_ex lw and sw
instructions rssign_exltlt2 branch instruction
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Adding in the MUXs (and control points)
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Control points
RegDst selects dest reg for write, selects rd
(R-format) when 1 and rt (for
lw) when 0 RegWrite enables value to be written
into register file ALUSrc selects ALU source
either register file (for R-type)
or an address coming from the 16 lower
bits. MemToReg Selects data source written
into the register file from memory (1) or
from ALU output (0) MemRead Active whenever
memory read is required (ie lw). MemWrite Active
only on a memory write (ie sw) Branch controls
PCSrc to select input to the PC
either the next instruction or the branch
address. ALUop1, ALUop2 Input to the ALU decode
logic
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Multicycle Control
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An Alternative MultiCycle DataPath
A-Bus
B Bus
A
Reg File
IR
mem
P C
inst mem
next PC
S
B
ZX
SX
W-Bus

• In each clock cycle, each Bus can be used to
  transfer from one source
• µ-instruction can simply contain B-Bus and W-Dst
  fields

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What about a 2-Bus Microarchitecture (datapath)?
Instruction Fetch
A-Bus
B Bus
A
Reg File
IR
P C
next PC
S
Mem
M
B
ZX
SX
Decode / Operand Fetch
A
Reg File
IR
P C
next PC
S
Mem
M
B
ZX
SX
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Control
Design of an ALU control circuit, in terms of the
instruction
Several layers of control
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ALU control circuit
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Control Unit
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Actions enabled on a given instruction
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Control Unit
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State Machine
1.Instruction Fetch
2. Decode/Register Fetch
Opjump
start
Opbeq
5. Write Register
OpR-type
4. Mem Access
3. ALU
MemWrite
IorD1
5. Write Register
Oplw/sw
Opsw
MemRead

IorD1
Oplw
3. ALU - Mem Addr Calc
4. Mem Access
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Microprogramming

• What are the microinstructions ?

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Designing a Microinstruction Set

• 1) Start with list of control signals
• 2) Group signals together that make sense (vs.
  random) called fields
• 3) Places fields in some logical order (e.g.,
  ALU operation ALU operands first and
  microinstruction sequencing last)
• 4) Create a symbolic legend for the
  microinstruction format, showing name of field
  values and how they set the control signals
• Use computers to design computers
• 5) To minimize the width, encode operations that
  will never be used at the same time

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Microprogramming
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Macroinstruction Interpretation
User program plus Data this can change!
Main Memory
ADD SUB AND
. . .
one of these is mapped into one of these
DATA
execution unit
AND microsequence e.g., Instr Fetch
Decode/Reg Fetch Execute (AND)
Write register
control memory
CPU
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Horizontal vs. Vertical Microprogramming
Most microprogramming-based controllers vary
between Horizontal organization (1 control
bit per control point) Vertical
organization (fields encoded in the control
memory and must be decoded to control something)
NOTE previous organization not TRUE
horizontal microprogramming register decoders
encoded microoperations
Vertical easier to program, not very
different from programming a RISC
machine - extra level of decoding may
slow the machine down
Horizontal control potential parallelism
of operations in the datapath - uses up
lots of control store
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Microinstruction format
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Start w/ control signals, grouped into fields

• Signal name Effect when deasserted Effect when
  assertedALUSelA 1st ALU operand PC 1st ALU
  operand RegrsRegWrite None Reg. is written
  MemtoReg Reg. WriteDataInp ALU Reg.
  WriteDataInp Memory RegDst Reg. dest. no.
  rt Reg. dest. no. rdMemRead None Memory at
  address is read, MDR lt MemaddrMemWrite Non
  e Memory at address is written IorD Memory
  address PC Memory address SIRWrite None IR
  lt MemoryPCWrite None PC lt PCSourcePCWriteCond
  None IF ALUzero then PC lt PCSourcePCSource
  PCSource ALU PCSource ALUout

Single Bit Control
Signal name Value Effect ALUOp 00 ALU adds
01 ALU subtracts 10 ALU does function
code 11 ALU does logical OR ALUSelB 000 2nd ALU
input Regrt 001 2nd ALU input 4
010 2nd ALU input sign extended IR15-0
011 2nd ALU input sign extended, shift left 2
IR15-0 100 2nd ALU input zero extended
IR15-0
Multiple Bit Control
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Legend of Fields and Symbolic Names

• Field Name Field Values Function of Field
  with Specific ValueALU Add ALU adds Sub ALU
  subtracts Func code ALU does function
  code Or ALU does logical ORSRC1 PC 1st ALU
  input PC rs 1st ALU input RegrsSRC2 4 2nd
  ALU input 4 Extend 2nd ALU input sign ext.
  IR15-0 Extend0 2nd ALU input zero ext.
  IR15-0 Extshft 2nd ALU input sign ex., sl
  IR15-0 rt 2nd ALU input Regrtdestination r
  d ALU Regrd ALUout rt ALU Regrt ALUout
  rt Mem Regrt Mem Memory Read PC Read
  memory using PC Read ALU Read memory using ALU
  output Write ALU Write memory using ALU
  outputMemory register IR IR MemPC
  write ALU PC ALU ALUoutCond IF ALU Zero then
  PC ALUoutSequencing Seq Go to sequential
  µinstruction Fetch Go to the first
  microinstruction Dispatch Dispatch using ROM.

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Microprogram it yourself!

• Label ALU SRC1 SRC2 Dest. Memory Mem. Reg. PC
  Write Sequencing
• Fetch Add PC 4 Read PC IR ALU Seq Add PC Extshf
  t Dispatch
• Lw Add rs Extend Seq Read ALU Seq
  rt MEM Fetch
• Sw Add rs Extend Seq Write ALU Fetch
• Rtype Func rs rt Seq rd ALU Fetch
• Beq Subt. rs rt ALUoutCond. Fetch
• Ori Or rs Extend0 Seq rt ALU Fetch