Logic decomposition during technology mapping

1
Logic decomposition during technology mapping

• Speaker David Bañeres Besora
• Department LSI
• Date 16/10/2002

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Index

• Introduction
• Synthesis of logic networks
• What is technology mapping ?
• Graph-Mapping and dynamic decomposition
• Implementation
• Conclusions
• Current work

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Introduction (1/3)
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Introduction (2/3)
CELLS COST SYMBOL
PATTERN
INVERTER 2
NAND2 3
NAND3 4
NAND4 5
AOI21 4
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Introduction (3/3)
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Introduction (3/3)
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Process of synthesis

• Synthesis is the process that, for a given
  network and a library cell, it returns a new
  network logically equivalent to the first, but it
  only uses cells of library and this network is
  optimised for delay or area.

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Phases of synthesis (1/3)

• Independent transformations

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Phases of synthesis (1/3)

• Independent transformations

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Phases of synthesis (1/3)

• Independent transformations

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Phases of synthesis (1/3)

• Independent transformations

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Phases of synthesis (1/3)

• Independent transformations

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Phases of synthesis (1/3)

• Independent transformations

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (2/3)

• Decomposition using base functions
• Decompose to a network NAND2/NOT

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Phases of synthesis (3/3)

• Technology mapping
• Greedy search

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Phases of synthesis (3/3)

• Technology mapping
• Greedy search

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Phases of synthesis (3/3)

• Technology mapping
• Greedy search

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Phases of synthesis (3/3)

• Technology mapping
• Using principle of optimality

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Phases of synthesis (3/3)

• Technology mapping
• Using principle of optimality

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Phases of synthesis (3/3)

• Technology mapping
• Using principle of optimality

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e
f
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What is technology mapping ?

• Technology mapping is the problem of optimising a
  network for area or delay, using only library
  cells.

library
Network returned
Network
rule
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Tree-Mapping

• It uses principles of optimal code generation
  using tree expressions Aho,Johnson

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Graph-Mapping

• Designed by Eric Lehman i Yosinori Watanabe
• IEEE Transaction on CAD, 1997
• Improvements
• It makes first and second phase of synthesis
  during technology mapping.
• It finds patterns in the original network and in
  all possible representations of the logic
  function that represents the network.

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Data structure used (1/2)

• Mapping graph
• Graph of ugates.
• Ugates
• Representation of a logic function and its
  complement. It contains all possible
  decompositions of the function.

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Data structure used (2/2)
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Data structure used (2/2)
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Data structure used (2/2)
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?-Mapping (1/2)

• It transforms the given network to an AND/NOT
  Netwok.

• It transforms the network to a mapping-graph.

• It reduces the graph

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?-Mapping (2/2)
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Dynamic decomposition (1/2)

• Application of distributive property.

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Dynamic decomposition (2/2)
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Dynamic decomposition (2/2)
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Dynamic decomposition (2/2)
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Mapping algorithms

• Graph-Mapping
• It doesnt apply dynamic decomposition
• Topological order of ugates
• ?-Mapping
• It applies dynamic decomposition
• Graph-Mapping is a subprocess

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Matching algorithm partial matches (1/2)

• We get all patterns and subpatterns for each
  library cell.

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Matching algorithm partial matches (2/2)
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Matching algorithm partial matches (2/2)
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Matching algorithm partial matches (2/2)
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Matching algorithm partial matches (2/2)
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Implementation

• Implementation of algorithm of Graph-Mapping with
  dynamic decomposition in SIS.
• Calculation of area and delay costs.

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Conclusions

• Advantage
• ?-Mapping is better than tree-based algorithm
  because it searches in all possible
  representations of the given network.
• Disadvantage
• ?-Mapping searches in more solutions but its CPU
  time is also greater.

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Current work

• Consider input delays.
• Implement Pareto-Points feature.
• Implement another algorithm of matching based in
  BDDs.
• Implement an algorithm for large libraries and
  networks.