Nanometer Device Scaling in Subthreshold Circuits

1
Nanometer Device Scaling in Subthreshold Circuits

• Scott Hanson, Mingoo Seok,
• Dennis Sylvester, David Blaauw
• University of Michigan, Ann Arbor

2
Exploring the Application Space
Reduce Vdd
Subthreshold Circuits
3
Subthreshold Basics
Drain Current in an NFET Device

• VddltVth
• Reduced Ion/Ioff
• Exponential with
• Vdd
• Vth
• SS
• Key challenges
• Modest performance
• Variability
• Robust memory design

4
Motivating Device Optimization

• Exponentially sensitive to device characteristics
• Subthreshold designers must be acutely aware of
  device characteristics
• Previous work
• Channel doping engineering (Paul, 2005)
• Drain/source underlap (Paul, 2006)
• Multi-gate devices (Kim, 2004) (Hanson, 2006)
• Use of RSCE (Kim, 2006) (Hanson, 2007)
• What will happen as device dimensions scale?
• Will conventional scaling be useful?
• Can scaling be re-optimized for subthreshold?

5
An Investigation of Subthreshold Scaling
SNM
Delay
Energy

• Two key deliverables
• Implications of current scaling trends
  onsubthreshold circuits
• Understanding of device optimization opportunities

6
Basic Device Modeling

• MEDICI model with four parameters Lpoly, Tox,
  Nsub, Nhalo
• All other dimensions proportional to Lpoly
• Halo/retrograde region modeled as Gaussian
  distribution

7
A Super-Vth Scaling Framework

• Goals
• Create 90nm 32nm baseline device models
• Closely mirror scaling of low standbypower
  device
• 30 reduction in Lpoly each generation
• 10 reduction in Tox each generation
• 100mV reduction in Vdd each generation
• Only used during optimization
• Affects SCE (and consequently halo implant)
• Nsub, Np,halo tuned to optimize delay subject to
  leakage constraint

8
Scaled Device Characteristics
G
G
S
D
S
D
9
Scaled Device Characteristics
Ss and Ion/Ioff at Vdd250mV

• SS increases by 10mV/dec
• Ion/Ioff reduces by 60
• Problematic for SRAM
• Leads to 10 reduction in SNM

10
Delay in Scaled Circuits
CMOS Inverter Delay

• Delay dominated by Vth, not Lpoly
• Sub-Vth design requires tight Vth control

11
Energy in Scaled Circuits
Energy for a Chain of 30 Inverters

• Energy improves with scaling
• Ss plays a prominent role in energy, delay

12
Opportunities for Improvement
Ss for a 45nm Device

• Key lessons
• SS is critical
• Lpoly scaling is not important
• Slow Tox scaling is important
• Opportunities
• Use increased Lpoly
• Use reduced doping
• Lets re-optimize our device

13
Optimization for Subthreshold
Scaling Factors in a 45nm Device
A Comparison of Optimized and Unoptimized Devices

• 20-25 reduction in Lpoly per generation
• Optimized device has nearly constant SS80mV/dec
• 19 improvement in SNM at 32nm

14
Revisiting Delay
CMOS Inverter Delay at Vdd250mV

• Comparison not strictly fair
• Re-optimization yields more gracefuldelay scaling

15
Revisiting Energy
Energy for a Chain of 30 Inverters

• Vmin nearly constant for optimized device
• Energy improves by 23 at 32nm

16
SNM in Scaled Subthreshold SRAM
60
17
Variability in Subthreshold SRAM

• Skew cell to a corner
• Failure at read SNM of 6 of Vdd
• Confidence at failure normalized to s

1 generation improvement
18
Read Current in Subthreshold SRAM
19
Future Device Optimizations
FIELDAY Simulations of 3 Devices

• New devices may offer some help
• High-? gate dielectrics
• Superior Ss
• Multi-gate devices
• Superior Ss
• Better SCE
• Light body doping

Courtesy of X. Wang, A. Bryant, IBM Originally
appeared in S. Hanson, et al., ISLPED 06
20
Some Final Thoughts

• Poor SS scaling (caused by slow Tox scaling)
  leads to problems
• Device scaling must be closely followed by
  subthreshold designers
• Vdd selection
• Delay optimization
• Memory design
• Simple modifications to doping and gate length
  may offer help
• Noise immunity
• Performance
• Energy consumption