ECE 715 VLSI Final Design Review

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ECE 715 VLSI Final Design Review

• Shift Register

David Faha Mark Whittenberger
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Contents

• Why a Shift Register
• Accomplishments
• Logical Designs
• Physical Designs
• What Is Left To Do
• Updated Schedule of tasks

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Why a Shift Register
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Why a Shift Register?

• A shift register will allow two different devices
  with different speeds to share a common memory
  structure.
• For the Fingerprint Recognition SoC project this
  register will allow the output of the spatial
  filter to run at the speed of the FFT core.
• This design can be made up of standard logic and
  will allow for integration into larger VLSI
  projects.

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Accomplishments
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Where Are We Now?

• Logical and Physical design for single bit
  shifting completed.
• Testing of the single bit shift design completed.
• Logical design of full structure has been
  designed.
• Physical design of full structure has been
  designed.
• Logical design of chip is finished.
• Physical layout of chip design is finished.
• Testing of the physical chip design is finished

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Logic Design of a Shift Register
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ADK D-Latch

• Reuse of existing designs
• Has existing characteristic information
• Modified to reduce routing of Data
• Standard design for Power and Ground allows for
  abutment of Latches

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Timing Issues

• Large Demand for Clock.
• Fan-out Issues due to large clock run.
• Since each stage is synchronous with the clock,
  propagation delay is simply the delay through 1
  D-Latch

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Physical Layout of D-Latch

• Modifications to D-Latch do not effect the
  operation of the D-Latch
• Standard D-Latch has been Modified for ease in
  routing with the use of Metal2 to eliminate the
  need for wire connections between latches
• Added Clock line in Metal 2 to provide complete
  functionality of the cell, with out the need for
  external wire connections and control of clock
  fan-out

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Physical Layout of D-Latch (2)
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Logical Layout of Single Bit

• In order to maximize the space, and to minimize
  the amount of routing necessary, both the logical
  and physical designs used the out and back
  design method

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Physical Layout of Single Bit

• Physical layout took a similar shape the logical
  design, which made it easier to keep track of the
  size and design of the physical layout.
• The physical layout and the logical layout grew
  in tandem so that LVS and DRC checks could made,
  and any errors more easily corrected.

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Physical Layout of Single Bit (2)
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Testing of Single Bit Design

• Testing of the initial structure has provided
  positive results up 512 Latches.
• Delay time from clock-pulse to output is only
  620ps.
• Data used for testing was 5ns skewed from the
  10ns giving half clock-period setup time for the
  first D-Latch.

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Simulation Results
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Logical Layout of Full Design

• Each grouping of 1024 D-Latches accounts for only
  1 bit.
• With the single bit accounted for the larger
  design for 32 bit could begin.

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Physical Layout of Full Design

• Full Design is in the same shape as the logical
  design.
• Size of full design in Massive.
• Design has passed LVS

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Images of Full Design(1)
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Images of Full Design(2)
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Images of Full Design(3)
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Design of Chip

• The chip design was taken from one of the smaller
  designs that was done to create the single bit
  design.
• Output ports were added to the design so that
  propagation through the chip could be viewed.
• 32 output test ports will be used.
• Chip design fits inside of pad frame.
• Testing of the chip design has begun with very
  positive results.

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Physical Layout of Chip
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Simulation of Chip Design
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Work to be Completed
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Work to be Completed

• Run a few more tests on the chip design.
• Connect the chip to the pad frame and pins.

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Time Table
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Updated Time Table