Hamming Code,Decoders and D,Tflip flops

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Hamming Code,Decoders andD,T-flip flops
Lecture 8

• Prof. Sin-Min Lee
• Department of Computer Science

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Decoders

• Next, well look at some commonly used circuits
  decoders and multiplexers.
• These serve as examples of the circuit analysis
  and design techniques from last lecture.
• They can be used to implement arbitrary
  functions.
• We are introduced to abstraction and modularity
  as hardware design principles.
• We often use decoders and multiplexers as
  building blocks in designing more complex
  hardware.

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What a decoder does

• A n-to-2n decoder takes an n-bit input and
  produces 2n outputs. The n inputs represent a
  binary number that determines which of the 2n
  outputs is uniquely true.
• A 2-to-4 decoder operates according to the
  following truth table.
• The 2-bit input is called S1S0, and the four
  outputs are Q0-Q3.
• If the input is the binary number i, then output
  Qi is uniquely true.
• For instance, if the input S1 S0 10 (decimal
  2), then output Q2 is true, and Q0, Q1, Q3 are
  all false.
• This circuit decodes a binary number into a
  one-of-four code.

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How can you build a 2-to-4 decoder?

• Follow the design procedures from last time! We
  have a truth table, so we can write equations for
  each of the four outputs (Q0-Q3), based on the
  two inputs (S0-S1).
• In this case theres not much to be simplified.
  Here are the equations

Q0 S1 S0 Q1 S1 S0 Q2 S1 S0 Q3 S1 S0
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A picture of a 2-to-4 decoder
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Enable inputs

• Many devices have an additional enable input,
  which is used to activate or deactivate the
  device.
• For a decoder,
• EN1 activates the decoder, so it behaves as
  specified earlier. Exactly one of the outputs
  will be 1.
• EN0 deactivates the decoder. By convention,
  that means all of the decoders outputs are 0.
• We can include this additional input in the
  decoders truth table

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An aside abbreviated truth tables

• In this table, note that whenever EN0, the
  outputs are always 0, regardless of inputs S1 and
  S0.
• We can abbreviate the table by writing xs in the
  input columns for S1 and S0.

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Blocks and abstraction

• Decoders are common enough that we want to
  encapsulate them and treat them as an individual
  entity.
• Block diagrams for 2-to-4 decoders are shown
  here. The names of the inputs and outputs, not
  their order, is what matters
• A decoder block provides abstraction
• You can use the decoder as long as you know its
  truth table or equations, without knowing exactly
  whats inside.
• It makes diagrams simpler by hiding the internal
  circuitry.
• It simplifies hardware reuse. You dont have to
  keep rebuilding the decoder from scratch every
  time you need it.
• These blocks are like functions in programming!

Q0 S1 S0 Q1 S1 S0 Q2 S1 S0 Q3 S1 S0
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A 3-to-8 decoder

• Larger decoders are similar. Here is a 3-to-8
  decoder.
• The block symbol is on the right.
• A truth table (without EN) is below.
• Output equations are at the bottom right.
• Again, only one output is true for any input
  combination.

Q0 S2 S1 S0 Q1 S2 S1 S0 Q2 S2 S1
S0 Q3 S2 S1 S0 Q4 S2 S1 S0 Q5 S2 S1
S0 Q6 S2 S1 S0 Q7 S2 S1 S0
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So what good is a decoder?

• Do the truth table and equations look familiar?
• Decoders are sometimes called minterm generators.
• For each of the input combinations, exactly one
  output is true.
• Each output equation contains all of the input
  variables.
• These properties hold for all sizes of decoders.
• This means that you can implement arbitrary
  functions with decoders. If you have a sum of
  minterms equation for a function, you can easily
  use a decoder (a minterm generator) to implement
  that function.

Q0 S1 S0 Q1 S1 S0 Q2 S1 S0 Q3 S1 S0
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Design example addition

• Lets make a circuit that adds three 1-bit inputs
  X, Y and Z.
• We will need two bits to represent the total
  lets call them C and S, for carry and sum.
  Note that C and S are two separate functions of
  the same inputs X, Y and Z.
• Here are a truth table and sum-of-minterms
  equations for C and S.

C(X,Y,Z) ?m(3,5,6,7) S(X,Y,Z) ?m(1,2,4,7)
0 1 1 10
1 1 1 11
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Decoder-based adder

• Here, two 3-to-8 decoders implement C and S as
  sums of minterms.
• The 5V symbol (5 volts) is how you represent
  a constant 1 or true in LogicWorks. We use it
  here so the decoders are always active.

C(X,Y,Z) ?m(3,5,6,7) S(X,Y,Z) ?m(1,2,4,7)
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Using just one decoder

• Since the two functions C and S both have the
  same inputs, we could use just one decoder
  instead of two.

C(X,Y,Z) ?m(3,5,6,7) S(X,Y,Z) ?m(1,2,4,7)
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Multiplexers

• A combinational circuit that selects info from
  one of many input lines and directs it to the
  output line.
• The selection of the input line is controlled by
  input variables called selection inputs.
• They are commonly abbreviated as MUX.

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Combinational circuit implementation using MUX

• We can use Multiplexers to express Boolean
  functions also.
• Expressing Boolean functions as MUXs is more
  efficient than as decoders.
• First n-1 variables of the function used as
  selection inputs last variable used as data
  inputs.
• If last variable is called Z, then each data
  input has to be Z, Z, 0, or 1.

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Karnaugh Map Method of Multiplexer Implementation
Consider the function
A is taken to be the data variable and B,C to be
the select variables.
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Example of MUX combo circuit

• F(X,Y,Z) Sm(1,2,6,7)

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4 Basic types of Flip-Flops

• SR, JK, D, and T
• JK ff has 2 inputs, J and K need to be asserted
  at the same time to change the state
• D ff has 1 input D (DATA), which sets the ff when
  D 1 and resets it when D 0
• T ff has1 input T (Toggle), which forces the ff
  to change states when T 1
• SR ff has 2 inputs, S (set) and R (reset) that
  set or reset the output Q when asserted

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Gated D-Latch

• Ensures S and R inputs never equal to 1 at the
  same time
• Useful in control application where setting or
  resetting a flag to some condition is needed
• Stores bits of information
• Constructed from a gated SR latch and a Data
  latch

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Analysis of Sequential Systems

• Goal
• Decide the timing and functional behavior from
  the implementation of a sequential system
  composed of FFs and logic gates
• Types
• Functional analysis
• Timing analysis

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Characteristic Equation of FFs
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D Flip-Flop
Q Next State
Characteristics ?Synchronous ?Avoids the
instability of RS flip-flop ?Retains its last
input value To set the ff, place 1 on D input
and pause the CK input To reset, place 1 on D
input and pause the CK input
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T Flip-Flop
T 1 force the state change T 0 state remain
the same
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T
CLK
Q1
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T
CLK
Q1
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How to use D to implement T Flip-Flop
D TQ TQ
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How to use D to implement T Flip-Flop
D TQ TQ
T
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How to use T to implement D Flip-Flop
T DQ DQ
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How to use T to implement D Flip-Flop
T DQ DQ
D
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Edge and level-triggered Flip Flop

• Digital circuit often form loops, flip-flops
  oscillations can
• Oscillation will not occur because by the time an
  output change cause an input change, the
  activating edge of the CK signal will be gone
• Positive edge triggered ff responds to a
  positive going edge of clock
• Negative edge triggered responds to a
  negative-going edge