SOC Design Flow Poster Introductions

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SOC Design FlowPoster Introductions

• Rhett Davis
• BWRC Summer 2000 Retreat

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The Search for a Group Name

• Early Candidates
• IC Design Flow
• Red Button
• Rhetts Button
• ICMake (EE-keh-MAH-kee)

3
Another Alternative
Realization andHardwareEmulation ofTransceiver
Targets using DesignAndVerification
ofIntegratedSystems
RHETT DAVIS
Vetoed by Group Leader
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Final Consensus
after several beers at Jupiter in honor of
the new Samuel L. Jackson movie
SSHAFT Simulink-to-Silicon Hierarchical Automated
Flow Tools
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Simulink-to-Silicon Chip Assembly

• Floorplanning / P R Design Flow
• Test Chip Complexity Statistics
• Complex MAC Comparison

by Rhett Davis
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BEE (Biggascale Emulation Engine)

• Automated inter- and intra- FPGA netlist
  generated from IC Flow description
• Place and Route Algorithm of FPGA partitions
• Potential BEE local interconnect architecture

by Hayden So
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An Algorithm/Architecture Co-Design Methodology
for Wireless Digital Receivers

• Architecture Exploration
• Performance Estimationfrom Simulink
• Design Example

by Ning Zhang
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Low Energy Clocked Storage Elements

• Flip-Flop Timing Characterization (Voltage
  Scaling)
• Energy Comparisons of 5 Flip-Flops
• Clock Power Analysis for Test Chip

by Dejan Markovic
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Methodology for Low-Energy Clock Distribution

• Approach to Reducing Energy Consumption
• Buffer Modeling and Characterization
• Buffer Selection Strategy

by Fred Chen
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• Implementation of new back-end styles
• Matching fixed-point types

By Nathan Chan, Ben Coates,
and Dave Wang
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