From Asynchronous Cellular Automata to Nanocomputers

1
From Asynchronous Cellular Automata to
Nanocomputers

• Ferdinand Peper

• National Institute of Information and
  Communications Technology (NICT),
• Nano ICT Group, Kobe, Japan
• University of Hyogo, Division of Computer
  Engineering, Himeji, Japan

Communications Research Laboratory (CRL),
Nanotechnology Group Himeji Institute of
Technology, Dept. of Electrical Engineering
2
Down to Nanometers
1mm
0.1mm
0.01mm
1µm
0.1µm
0.01µm
1nm
0.1nm
3
Moores Law
of transistors on chip doubles every 18 months
Combination of increases in transistor densities
and increases in chip sizes
History
(1965) Doubling every 12 months
(1975) Doubling every 24 months
(1980s) Doubling every 18 months
Factors change devices, design, architectures
4
Von Neumann Architecture
CPU
Memory

• Program stored in memory like data (Neumann,
  etc. 1949)

5
Von Neumann Architecture

• Bottleneck between CPU and Memory

? Wiring not local ? much chip area for wiring

• Irregular structure

? Design manpower required
3 year design staff
Million Transistors
? Complicates manufacturing
Increasingly Problematic as Integration Density
Rises
6
Top-down Manufacturing

• Uses a Master Scheme
• Any structure possible (irregular)
• Lower limit to feature sizes

7
Bottom-up Manufacturing
Self-Assembly
Directed Self-Assembly
Molecular Self-Organization
Molecular Pattern Matching
Styreneline Wolkow, 2000
DNA Tiles Yan et al., 2003
Regular / random structures
(Semi-) regular structures
Basically dumb materials
Some functionality
8
Random and Regular Structure
Regular structure
Random structure

• Configuration needed
• Configuration may include defect-tolerance
• Easier to make
• Harder to use

• Configuration needed
• Defect-tolerance separate issue
• May be harder to make
• Easier to use

Cellular Automata
Neural Networks, Swarms
9
Computer Architectures Timing

• Acceptance of synchronous timing (early 1950s)

Problems
? Only 1 of transistors used simultaneously,
but all draw power ? Heat dissipation !
? Wire delays become increasingly important
Clock does not scale
with integration
Should we go back to asynchronous timing?
10
Heat Dissipation
Asynchronous timing

• Clocking on nanometer scales difficult
• Heat dissipation at high integration densities

Advantages of Asynchronous Circuits become
clearer with higher integration densities
11
Asynchronous Cellular Automata
12
Synchronous Cellular Automaton
Update All Cells at the Same Time
13
Simulating SCA on ACA

• Cells are randomly selected to be updated
• Every cell gets timer counting 0?1?2?0...
• Every cell remembers previous and current state
• If cell is 1 step ahead of any neighbor, it will
  not be updated, even when selected
• O(3n2) states Nakamura,74
• O(n22n) states Lee,04

From Lee et al.,04
14
Simulation on Asynchronous Cellular Automaton
(ACA)
Update Each Cell at Random Times
15
Which CA are Useful for Nanocomputing?

• Direct asynchronous implementations in which only
  cells near signals are active
• Low complexity of cells
• Few states
• Few transition rules (no central rule table)

16
Timing in ACA
A CA is restricted asynchronous if at each time
step at most one cell that is randomly selected
from the cell space undergoes a state transition
A CA is completely (or purely) asynchronous if
at each time step each cell in the cell space has
a certain probability p (0 lt p lt 1) to undergo a
state transition, which is independent of the
other cells
17
Signal Transmission on Asynchronous CA
Transition rules applied with certain
probability when Left-Hand-Side matches pattern
in cell space
18
Design Principles of ACA (1)

• Serialize transitions critically dependent on
  update ordering

• Sheath of signal cannot advance first otherwise
  mess
• Controlled advance of kernel

Advance of temporary kernel state Advance of
sheath along it Permanent advance of kernel
19
Design Principles of ACA (2)

• Temporal blocking of a cells update until its
  neighborhood
• matches Left-Hand-Side of a transition rule

• Upon advance of kernel, advance of tail is
  unblocked
• Rear / side of tail cleared after center part
• of tail has advanced

Order of clearing unimportant
20
Design Principles of ACA (3)

• Reverse rules for deadlock situations
  (backtracking)

Note Rules are applied with probability p lt 1
Deadlock
This is impossible for synchronous cellular
automata
21
Signal Transmission on Asynchronous CA
Transition rules applied with certain
probability when Left-Hand-Side matches pattern
in cell space
6
4 4
6
1
1
2
3
4
5
1
1
6
6
4 4
Semi-totalistic asynchronous CA with 3 states,
Moore neighborhood and 6 transition rules Adachi
et al., 2004
22
Chimp signal Rule 1
23
Chimp signal Rule 2
24
Chimp signal Rule 3
25
Chimp signal Rule 4
26
Chimp signal Rule 5
27
Chimp signal Rule 6
28
Chimp Signal - Rules
29
Transmitting sequence of signals
30
Crossing Signals

• Signals negotiate with each other for passage
  (arbitration)
• Arbitration possible due to asynchronous updating

31
Computation on Asynchronous Cellular Automata
Computation Problem
Convert Problem into Circuit
Cellular Automaton (CA)
Robust to signal delays in lines or components
32
Nanocomputer Operations
Alternative operational principles

• Signal propagation and interaction by different
  mechanisms like molecular interactions (e.g.
  Token-Based)

33
What is a Token?

• Abstract unit of information used for passing a
  message between devices

How to Represent it?

• Indivisible discrete unit
• Numbers of tokens change only as result of
  operations

34
Signals are Tokens
Particles
Cascades
Interaction-based signals
Ballistic signals
35
The Gauss Rifle
http//www.scitoys.com/scitoys/scitoys/magnets/gau
ss.html
36
Operation of Gauss Rifle
http//www.scitoys.com/scitoys/scitoys/magnets/gau
ss.html
It Amplifies!
37
Our Own Gauss Rifle
38
Signal Propagation by Gauss Rifle
Potential Energy Decreases
Not reusable unless initial state is restored To
restore initial state pump energy in system
39
Toppling dominoes
Thanks to Jordi Cortadella
40
Wire
Output
Input
Thanks to Jordi Cortadella
41
OR gate
Output AB
Input B
Input A
Thanks to Jordi Cortadella
42
Molecule Cascades -- IBM
Heinrich, Lutz, Gupta, Eigler, Science, 15 Nov
2002, pp. 1381-1387
http//domino.research.ibm.com/Comm/bios.nsf/pages
/cascade.html
Hopping CO molecules on Cu(111) surface
43
Tilting of Molecules
Repulsive
O
C
Cu
Attractive
(side view)
(top view)
Carmona et al., 2006
CO molecules next to each other are
repulsed. Depending on presence of other CO
molecules, this may result in one moving away
from the other
44
Linked Chevron Cascade -- IBM
45
AND-Gate -- IBM
Input X
Output
Input Y
46
OR-Gate -- IBM
Output
Input X
Input Y
47
Scanning Tunneling Microscope (STM)

• Tunneling rate extremely sensitive to distance
  changes
• Can also pick up atoms or molecules

Michael Schmid, IAP/TU Wien
48
Molecule Cascade Video -- IBM
http//domino.research.ibm.com/Comm/bios.nsf/pages
/cascade.html
49
Three-input sorter Area 200 nm2 (545 CO
molecules) Equivalent CMOS circuit
53µm2 260,000 times smaller !!! Moores law
45 years to achieve the same size Delay
1 hour at 5 K
Thanks to Jordi Cortadella
50
Molecule Cascade Challenges

• Only one-time computing
• Reinitialize after operation
• or reverse operation?
• Finding suitable configurations

Joint work with Jordi Cortadellas group
at University Polytecnica Cataluniya, Spain
51
Delay-Insensitive (DI) Circuits

• Asynchronous circuit of which correctness of
  operation is robust to signal delays
• Operations driven by signals

Receive Input Signals
Produce Output Signals
Inactive Wait
Circuit Element Processing Cycle
52
ACA-based circuit characteristics

• Signals have discrete character
• Each signal has position on a wire
• Signal cannot be cancelled
• More than 1 signal may be on wire

53
Join and Reset Functionalities
Join
Resettable Join

• Wait for all signals before
• proceeding

Redirect waiting signals
Reset table Join
Join
Rendez-vous, Synchronizing
54
DI-Circuit Primitives
a
b
c
FORK
a gives b and c
R-COUNTER (Resettable Modulo 2 Counter)

• Single a stays pending

• a,a gives b

MERGE
a or b gives c
55
DI-Circuit Primitives
a
k
b
r
b
c
FORK
a gives b and c
a
R-COUNTER (Resettable Modulo 2 Counter)

• Single a stays pending

• a,a gives b

• Single r stays pending

• a,r gives k

MERGE
a or b gives c
56
Triangular Resettable Join TRIA
Patra (93)
57
Construction of TRIA
58
Dual Rail Encoding

• Represent binary value by pair of wires

0
1
0
1
Spacer
Error
NOT-gate easy!
59
Delay-Insensitive 1-bit Memory
60
Self-Timed Cellular Automaton Signal Propagation
on STCA
Transition Rule
Cell
61
Fork
62
Merge
63
One-Bit Memory Writing
Write 1
Write 0
Acknowledge of Writing 1
Acknowledge of Writing 0
0-bit is Stored Here !
1-bit is Stored Here !
64
One-Bit Memory Reading
0-bit is Stored Here !
1-bit is Stored Here !
Reading out 1-bit
Reading out 0-bit
Read
65
Delay-Insensitive NAND-gate
a1 NAND
66
Dual-Rail Encoded NAND gate
Fork
TRIA
Merge
Hex semi-totalistic 6-state ACA Adachi et al.,
2004
67
Parallel Processing in DI Circuits
Arbitration Required
For greater efficiency Parallel processing
Arbitration Fair assignment of common
resources among competing processes
68
DI-Circuit Primitives
a
k
b
r
b
c
FORK
a gives b and c
a
R-COUNTER (Resettable Modulo 2 Counter)

• Single a stays pending

• a,a gives b

• Single r stays pending

• a,r gives k

MERGE

• a,a,r gives b (r pending)

a or b gives c
69
DI-Circuit Primitives
a
k
b
r
b
c
FORK
a gives b and c
a
R-COUNTER (Resettable Modulo 2 Counter)

• Single a stays pending

• a,a gives b

• Single r stays pending

• a,r gives k

MERGE

• a,a,r gives b (r pending)

a or b gives c
or k (a pending)
70
Rotary in Traffic
71
Crossing Signals - Principle
signal arrival registers

• Register arrival of signal
• Loop around to scan arrival
• If arrived, leave loop, let signal cross, reenter
  loop

registers scanning
Priese 78, JCSS, A Note On Asynchronous
Cellular Automata
72
Crossing Signals - Circuit
73
Crossing Signals
ain
bout
bin
aout
Hex semi-totalistic 6-state ACA Adachi et al.,
2004
74
Crossing Signals Other Model
Neumann neighborhood 5-state ACA Lee et al.,
2003
75
Conclusions

• For nanocomputer architectures, the CA we
  designed are still too complex
• Configuration has not been discussed

Self-Reproduction Techniques
76
ACA Research Themes

• How to configure circuits on cell space?
  Self-reproduction techniques (von Neumann)
• Fault Tolerance ? deal with noise
• Defect Tolerance ? deal with manufacturing
  defects
• Less states, less rules ? simpler cells
• Exploiting noise Brownian circuits

77
Acknowledgements
NICT Dr. Jia Lee, Dr. Susumu Adachi Univ. of
Hyogo Dr. Teijiro Isokawa, Prof. Nobuyuki Matsui
Hiroshima Univ. Prof. Kenichi Morita
78
Appendix
79
R-Counter
k
b
r
arbitration
a
80
Delay-Insensitive NAND-gate
a0 NAND