MuGFET v1.1

1
MuGFET v1.1

• First Time User Guide to MuGFET v1.1
• Nov., 17, 2008

2
Introduction

• Introduction
• Theory
• Rappture interface
• Examples
• Summary

3
Introduction
Size of device decreases (Moores Law)
?number of gates increases for more efficient
gate control
Nanoscale Multi-Gate Field Effect Transistor
FinFET
Nanowire FET
Gate
Insulator
Insulator
Channel
Channel
4
Introduction
Device size becomes nano-scale
which is close to the atomistic dimension.
?Quantum transport simulation is necessary,
but...
Relatively long and large device
quantum transport simulation is
not a good choice
? computationally very expensive
? difficult to include all the scattering
processes
Gate length 20100nm
Width 1050nm
5
Introduction
Drift diffusion type simulator is enough to
understand the characteristics of relatively long
and large devices
Why?
QM mechanics is not dominant if the lateral
dimension of the transistor is
larger than 10 nm
Not strictly valid but physical insight can be
provided
The subthreshold characteristic is still
diffusion dominated.
The on-current can never be overestimated by
drift diffusion simulation
Hot carrier transport can be taken care of by
solving energy balance equation
Drift diffusion simulator is way faster than the
quantum transport simulator.
Private communication with prof. Vasileska in ASU
6
PADRE and PROPHET
PROPHET general partial differential solver
developed at Bell Lab.
PADRE device simulator developed at Bell Lab.
https//www.nanohub.org/resource_files/tools/prop
het/doc/guide.html
http//www.nanohub.org/resource_files/tools/padr
e/doc/index.html
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Theory

• Introduction
• Theory
• Rappture interface
• Examples
• Summary

8
Drift Diffusion Picture
Self consistent calculation
scattering mobility
Poisson equation
Continuity equation
Source
Channel
Drain
transport direction
ECE612 Fall2008 lecture 8 note
R. F. Pierret, Semiconductor Device Fundamentals
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Energy Balance Equation
velocity overshoot
M.R.Pinto et. al. IEEE, 1993
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Rappture Interface

• Introduction
• Theory
• Rappture Interface
• Examples
• Summary

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Outline of Interface
Device Type ? Structure ? Material ? Environment
? Simulator ? Simulate
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Device Type
Class FinFET or Nanowire
Dimension
Nanowire-no dimension
Gate type - metal or poly(polysilicon)
(poly option is only valid in PADRE simulator.
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Device Structure

• Geometry-X Lateral Direction
• Channel width
• The width of silicon channel region
• Oxide thickness
• Left wall
• Right wall
• X-direction is radial direction
• when you choose the nanowire
• ? The cross section should be large compared to
  electron wave length so that quantum effect
  should not appear to use drift-diffusion
  equation.

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Device Structure

• Geometry-Y
• Lg gate length
• Ls source extension length
• Ld drain extension length
• Extension region has same width as the channel
  but, doped differently
  
• Os/Od Gate overlap to source/drain

Y.K.Choi et. al. IEEE Electron Device Letters,
2002
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Device Structure

• Geometry-Z
• Z directional geometry setting is only activated
  when you choose triple gate (3D) in device type
  
• Hch channel height
• Top_ox top oxide thickness
• Sub_ox substrate oxide thickness

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Doping

• Doping
• Doping concentration in each section
• Doping type in each section
• Gaussian Doping
• Gaussian doping profile starts from the end of
  the source/drain extension region
  
• Characteristic length is the length to which the
  doping drops by the factor exp(-1).

17
Material Property
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Environment
Drain bias
Source bias
Options for plot
Temperature of the environment
Icritical
Gate bias ramp on-off current is to be
calculated and plotted at the bias s
etup here
Vth
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Simulator Options - PROPHET

• Only Equilibrium
• When you want to simulate only equilibrium
  condition, the bias steps will be all ignored.
  
• Plot dimension
• 1D(x) 1D plot across the channel
• 1D(y) 1D plot along the channel
• 2D 2D plot
• Newton iteration parameters
• ? for convergence of the continuity equation
  and the poisson equation
  
• Maximum number of iteration
• Tolerance
• Models
• Quantum correction
• Lombardis transverse field dependent mobility
  model

Lombardis mobility model http//www-tcad.sta
nford.edu/prophet/user_ref/node8.html
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Simulator Options - PADRE

• Grid Preview
• The mesh structure can be seen before running
  simulation
  
• Models
• Statistics Fermi or Boltzmann
• Energy balance equation
• Solve energy balance equation for hot carrier
  transport to be included.
  
• Bandgap narrowing
• Concentration dependent mobility
• Nonlinear drift velocity field model
• Vertical field dependent mobility model
• Carrier carrier scattering model
• Impact ionization

http//www.nanohub.org/resource_files/tools/padre
/doc/padre-ref/models.html
http//www.nanohub.org/resources/1514/
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PADRE Option - Energy balance equation

• When energy balance equation is chosen to be
  solved, continuity equation, Poisson equation,
  and energy balance equation are coupled to each
  other and solved self-consistently.
• It is not easy to have them to be converged.
• Bias steps should be small when solving energy
  balance equation.
  
• Sometimes it is needed not to choose wide range
  of bias.
  
• Try to start from zero bias and increase it
  slowly.

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Useful Plots for Device Design

• IV characteristics
• Threshold voltage
• Subthreshold swing
• Transconductance
• Drain induced barrier lowering(DIBL)
• On/Off current and their ratio
• Doping, electron, hole density
• Electrostatic potential
• Energy band diagram
• Net charge density
• Electric field

These plots are supported only in PADRE
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Plots
Sequence plot for applied bias
3D plots are available but a little bit slow
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Examples

• Introduction
• Theory
• Rappture interface
• Examples
• Summary

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Example Loader
2. Click simulate
1. Choose
Retrieving database to plot the result without
simulation
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Example p-finFET Lg45nm, Wch30nm, tox2.5nm

• The primitive finFET structure
• Gaussian doping - using raised source and drain,
  dopants diffused to the source and drain
  extension region
  

dopants
dopants
Ls and Ld(source/drain extension length) is same
as spacer width.
Sub 50-nm finFET PMOS - Huang, et al.,
IEDM,1999
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Simulation Experiment Result Comparison Id-Vg
Vg(V)
On-current
?How to match experiment and simulation
Match off-current by changing workfunction of
gate material. Match on-current by changing the c
haracteristic length of Gaussian doping.
On-current is always underestimated
by drift diffusion simulation because the model
assumes velocity of electrons are saturated in
the channel
Id(A/µm)
Subthreshold slope match
For more accurate calculation, we need quantum
correction and energy balance equation to be
solved but, for now quantum correction is
supported by PROPHET and energy balance
equation(velocity overshoot) by PADRE
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Effect of Gaussian Doping Profile
Id-Vg characteristics
Doping Density
Id(A/µm)
along - channel(µm)
Electrostatic potential at equilibrium
Vg(V)
increase characteristic length
increase doping in the channel
decrease the potential in the channel
drain current increase
along -channel(µm)
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Channel Formation Quantum Correction
Electron density
Doping density
across channel
In PADRE and PROPHET, inversion charges are at
the surface of the channel
?Vth
In reality, because of quantum effect, the
carriers flow at a distance from the surface ?
threshold voltage changes
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Drain Current Normalization

• Normalization of Id (nanowireFET)
• Drain current is sometimes normalized to the
  diameter in experiment.
  
• Drain current in PADRE and PROPHET is not
  normalized.
  
• Comparison with experiment
• Divide by the diameter to the PADRE and PROPHET
  results
  
• Change the units to A/µm or µA/µm

• Normalization of Id (finFET)
• Normalization to the fin height
• Same as the conventional normalization to the
  width of the channel (PADRE and PROPHET)
  
• Normalization to the fin height 2
• Multiply 2 due to channel formation in both side
  walls
  
• Comparison with experiment
• Divide 2 to the PADRE and PROPHET result if
  experimental result uses normalization to the fin
  height2.
  

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Example p-finFET Lg60nm, Wch40nm, tox2.5nm
Id(A/µm)
on-current
Subthreshold slope match
Vg(V)
Experiment result from Y.K.Choi et. al. IEEE
Electron Device Letters, 2002
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Example - Nanowire
Vg(V)
PROPHET failed in nanowire simulation
Id(A/µm)
Subthreshold-well matched
Nanowire - quantum ballistic transport
simulation tool for nanowire structure - availabl
e in nanoHUB.org
Experiment -Sung DaeSuk, et al.,
IEDM 2005, pp 717-720, Dec 2005
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Example - Hot Carrier Transport Effect (Velocity
Overshoot)
Vg(V)
Id(A/µm)
Subthreshold degradation 61.1mv/dec ? 63.7mv/dec
Transconductance increases at high gate voltage
Threshold voltage change
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Short Channel Effect Nanowire/DG-finFET
Comparison
Vg(V)
Vd0.05
Id(A/?m)
MUGFET predict how the short channel nanowire
and DG-finFET behaves. As expected, nanowire is b
etter candidate to suppress the short channel
effect
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Overview

• Introduction
• Rappture interface
• Theory
• Results
• Summary

36
Summary
Drift-diffusion simulator MuGFET using PROPHET
and PADRE is upgraded to v1.1 Energy balance eq
uation option included to understand hot carrier
effect on transport Input interface upgraded fo
r users convenience Gaussian doping profile up
graded to be more realistic Minor error fixed
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Considered (Possible) Future Work

• 3D visualization (openDX)
• Refinement of 3D simulation
• Process simulation using PROPHET to feed in the
  result to PADRE
  
• ?reallistic doping and geometry
• AC response in PADRE
• Quantum correction is already implemented
• ?density gradient model in PROPHET
• ?balance equation model into PROPHET?
• Parallelization?new code?
• Modified drift diffusion model