Tradeoffs of Performance and Single Chip Implementation of Indoor Wireless MultiAccess Receivers

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Tradeoffs of Performance and Single Chip
Implementation of Indoor Wireless Multi-Access
Receivers

• Ning Zhang
• Prof. Robert Brodersen
• Berkeley Wireless Research Center
• June 1999

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System Overview

• Application
• Indoor, pico-cellular, wireless environment with
  slowly Rayleigh fading
• Downlink providing multimedia access to 20-30
  users with BER of 10-5
• Severe power consumption constraint on portable
  receiver
• System Specifications
• Total bandwidth 25MHz
• Total transmit power 1mW

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Mostly Digital Receiver Architecture
RF Filter

A/D Converter
Carrier and Timing Sync.
RF to Baseband
Data Demod. Detection
Analog IC
Digital IC

• Use system level design choices to simplify the
  analog front-end requirements and convert to
  digital domain as close as possible to antenna
• Direct conversion with 10-bit A/D
• Rely on advanced digital signal processing
  algorithms to compensate for channel impairments
  and analog circuitry limitations
• Low power digital design
• Ultimate objective fully integrated, single
  chip radio

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Design Methodology

• Design Space Explorations
• Algorithm level
• performance vs. implementation complexity
• Architecture level
• flexibility vs. energy efficiency
• Design Framework
• High level modeling and estimation
• Algorithm/Architecture level optimizations
• System/Hardware codesign

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Performance and Computational Complexity
Comparisons
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Architectural Choices
Arm8 (40MHz, 1V, 125MHz, 3.3V)
TI TMS320C54x (100MHz, 1.8V)
Custom Design (25MHz, 1V)
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Software Implementations
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Implementation Technology
.. Delay -. Energy --o Energy-Delay-Product
Supply Voltage (V)
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Hardware Implementations
For fixed sample rate of 0.8MHz Optimizations
include algorithm modifications and
transformations