The Crosspoint Queued Switch

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The Crosspoint Queued Switch
Yossi Kanizo (Technion, Israel)
Joint work with Isaac Keslassy (Technion, Israel)
and David Hay (Politecnico di Torino, Italy)
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Typical Switch Architectures
Linecards
Linecards
Switch Fabric
Switch Fabric
Assumes Instantaneous Closed Loop
CICQ Combined Input and Crosspoint Queued
IQ Input Queued
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Single-Rack Router

• Instantaneous closed loop ? works in a single
  rack
• Problem multi-rack routers

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Current Router Architectures
Is the closed loop still instantaneous?
Source N. McKeown
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Time Trends
ns
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Hiding Propagation Delays

• Traditional solutions
• Increase time-slot ? poor switch performance
• Hide propagation delays using buffers ?
  impractical amount of buffering
• Proposed solution closed loop ? open loop
• Performance degradation vs. instantaneous closed
  loop

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Outline

• CQ Open-loop switch architecture
• Performance Evaluation
• Analytical results
• Simulations

? CQ performance degradation is not significant
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Proposed ArchitectureThe Crosspoint-Queued (CQ)
Switch
Linecards
Switch Core

• No queues in the linecards
• Buffering only inside the fabric
• Independent output schedulers
• Drops with full buffers

10s of meters
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CQ Properties

• Open loop
• No communication overhead
• No linecard queues
• No linecard queue management
• Router on a chip
• Buffering and switch fabric on same chip

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Why not 10 years ago?

• No need single rack
• No technology SRAM density
• Moores law density doubling every 2.5 years
• Aggressive 128x128 CQ switch 4 cells of 64 bytes
  per crosspoint ? 64 cells today
• Conservative buffer requirements
• TCP Stanford model with smaller buffer needs
  Appenzeller, Keslassy and McKeown 04

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Outline

• CQ Our open-loop switch architecture
• Performance Evaluation
• Analytical results
• Simulations

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100 Throughput as B?
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• Throughput boundsOQ(2B-1) CQ(B) OQ(NB)

100 Throughput
100 Throughput
100 Throughput
Buffer size B, LQF scheduling algorithm
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Uniform Traffic, B1

• Uniform traffic model
• At each time-slot, at each of the N inputs
  Bernoulli IID packet arrivals with probability
  ?.
• Each packet is destined for one of the N outputs
  uniformly at random
• Theorem Under uniform traffic and B1, the
  performance of the switch is independent of the
  specific work-conserving scheduling algorithm
• Intuition Symmetry

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Uniform Traffic, B1

• Theorem The throughput and waiting time of a CQ
  switch, B1 is
• Proof Based on Z-transform

q1-r/N
Goes to 100 as N goes to infinity
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Models for larger buffers

• Approximate Performance Analysis
• Model for exhaustive round-robin scheduling
• Based on modifications to polling system with
  zero switch-over times
• Model for random scheduling algorithm
• Show 100 throughput as N?8

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Trace-Driven Simulation
32x32 CQ switch with different buffer sizes (in
units of 64-byte packets)
Buffers of size 64 suffice to ensure 99
throughput for N32.
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Conclusions

• CQ is open loop ? allows multi-rack configuration
• CQ provides easy scheduling
• CQ is feasible to implement in a single chip
• CQ shows good performance in simulations

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Thank You