PRARDIVA MANGILIPALLY

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32 BIT PARALLEL LOAD REGISTER WITH CLOCK
GATING

• PRARDIVA MANGILIPALLY
• ELEC 6270

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OUTLINE

• Objective
• Basic idea
• Basic gating circuit
• Modified clock gating circuit
• Design platform
• Results
• Conclusion

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OBJECTIVE

• To measure the average power for a 32 bit
  parallel load register with and without clock
  gating.
• To compare the results for the same.
• To study the effect of clock gating on power
  consumption for a 32 bit parallel load register.

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CLOCK GATING

• Clock gating is one of the power saving
  techniques in which additional logic is added to
  a circuit to prune the clock tree ,thus disabling
  portions of circuitry so that flipflops do not
  change state.As a result switching power goes to
  zero.

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MODIFIED CLOCK GATING CIRCUIT
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Design platform

• Latchfree clock gating circuit
• Tools used Modelsim, leonardo, Design Architect,
  Eldo
• Technology tsmc018
• Clock frequency 50MHz
• Operating voltage 1.8V

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Pattern0000000

• Without clock gating
• Average power 242.6818U W

• With clock gating
• Average power 42.8374U W

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Pattern111111111

• Without clock gating
• Average power 244.0567UW

• With clock gating
• Average power 27.4138UW

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Pattern101010

• Without clockgating
• Average power457.2622uW

• With clock gating
• Average power 628.8430U W

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PATTERN10111011

• WITHOUT CLOCKGATING
• AVERAGE POWER357.8213UW

• WITH CLOCK GATING
• AVERAGE POWER337.1065UW

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PATTERN01000100

• WITHOUT CLOCKGATING
• AVERAGE POWER355.11064UW

• WITH CLOCKGATING
• AVERAGE POWER331.2031UW

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PATTERN11011101

• WITHOUT CLOCKGATING
• AVERAGE POWER352.7703UW

• WITH CLOCKGATING
• AVERAGE POWER324.1347UW

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PATTERN00100010

• WITHOUT CLOCKGATING
• AVERAGE POWER344.7696UW

• WITH CLOCKGATING
• AVERAGE POWER337.4078UW

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INPUT12000000101000000101010000000000000000000000
00000000

• WITHOUT CLOCK GATING
• AVERAGE POWER288.4402UW

• WITH CLOCK GATING
• AVERAGE POWER165.1852UW

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INPUT12 11111111101010111111010111111111111111111
111111111

• WITHOUT CLOCKGATING
• AVERAGE POWER289.1212UW

• WITH CLOCKGATING
• AVERAGE POWER146.8568UW

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Power Reductions
Without clock gating With clock gating
TRANSITION DENSITY EXPECTED POWER (UW) OBSERVED POWER (UW) EXPECTED POWER (UW) OBSERVED POWER (UW) POWER REDUCTION ()
0.0000 244.0512 244.0567 68.7008 27.4138 88.77
0.0004 242.6944 242.6818 70.1134 42.8374 82.35
0.1000 262.4961 289.1212 182.0272 146.8568 49.21
0.1024 289.1168 288.4402 170.3126 165.1852 42.73
0.2500 357.7568 357.8213 340.1931 337.1065 5.51
0.5000 457.1456 457.2622 655.6832 628.840 -37.5
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CONCLUSIONS

• Clock gating technique effectively reduces
  dynamic power in most of the cases.
• However,it increases power when there are
  transitions in every clock cycle.This increase is
  due to the extra power consumed by the ex-nor and
  nor gates in the clock gating circuit which
  account to about 58 increase in total hardware.
• If this increase in hardware could be reduced
  then the power savings can be increased even in
  the worst case which calls for the implementation
  of a different clock gating circuit or the usage
  of low power ex-ors discussed in the class.

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REFERENCES

• Class lecture slides at http//www.eng.auburn.edu
  /vagrawal/ COURSE/ E6270_Spr09/course.html
• Frank Emnett and Mark Biegel, Power Reduction
  Through RTL Clock Gating, SNUG2000(This paper
  discusses a method to avoid premature truncation
  of the clock).

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THANK YOU