ENGR 4862 Microprocessors Lecture 28

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ENGR 4862 MicroprocessorsLecture 28
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Other Supporting Chips

• 74LS373 Latch
• Provide isolation and bus boosting
• 74LS244 Unidirectional data transceiver chip
• 74LS245 Bidirectional data transceiver chip
• Provide bus buffering and boosting
• 8288 Bus Controller
• A 20-pin chip to provide all the control signals
  when the 8086/88 is in the maximum mode
• 8284 Clock Generator

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8086/8088 in Max Mode
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8288 Bus Controller
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The Clock

• The clock signal is very important to the
  operation of a microprocessor circuit
• It synchronizes the sequential activities of the
  CPU and the system
• Not all devices use a clock signal (eg. PPI)

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8284 Clock Generator and Driver (I)

• The 8088/8086 CPUs require a specific waveform
  for the system clock
• Fast rise and fall times (lt10ns)
• Logic 0 -0.5 to 0.6 V
• Logic 1 3.9 to 5.0 V
• Duty cycle of 33

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8284 Clock Generator and Driver (II)
33 Duty Cycle
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8284 Clock Generator
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8284 Clock Generator and Driver (III)

• The 8284 provides a proper clock signal
• Uses a crystal oscillator (3 oscillations per
  clock)
• Provides correct waveforms for other signals to
  CPU
• RESET
• READY (request for wait states)

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8284 Clock Generator and Driver (IV)

• An 18-pin chip. Not only provide the clock and
  synchronization for the microprocessor, but also
  provides the READY signal for the insertion of
  wait states into the CPU bus cycle
• Input Pins
• RES (Reset In) from power supplier
• X1 and X2 (Crystal In) the crystal frequency
  must be 3 times the desired frequency for the
  microprocessor
• For IBM PC, 14.31818 MHz (max 24 MHz)
• RDY1 and AEN1 provide a Ready signal to the uP,
  which will insert a wait state to the CPU
  read/write cycle
• RDY2 and AEN2 For multi-processor systems

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8284 Clock Generator and Driver (V)

• Output Signals
• RESET reset signal to the 8086/88, activated by
  RES
• OSC (oscillator) provided to the expansion slot
• CLK (clock) 1/3 of the OSC or EFI input, with a
  duty cycle of 33
• In IBM PC, OSC 14.31818 MHz, so CLK 4.772776
  MHz
• PCLK one-half of CLK (1/6 of crystal) with duty
  cycle of 50 and is TTL compatible. Provided to
  8253 Timer to generate speaker tones
• READY connect to READY input of CPU to insert
  wait states

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Machine Cycles

• Also Bus Cycles
• Definition
• One discrete information transfer on the buses
• This includes the address, data, and control
  information

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Machine Cycles

• A machine (bus) cycle consists of at least four
  clock cycles, called T states
• A specific defined action occurs during each T
  state (labeled T1 T4)
• T1 Address is output
• T2 Bus cycle type (Mem/IO, read/write)
• T3 Data is supplied
• T4 Data latched by CPU, control signals
  removed