Ch'6 Logic Verification

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Ch.6 Logic Verification
Standard Cell Design
TAIST ICTES Program VLSI Design
Methodology Hiroaki Kunieda Tokyo Institute of
Technology
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Design Verification

• How to confirm the correctness of design result
• 50-70 of design period is used for design
  verification.
• Methods
• Logic Simulation and Emulation
• Formal Verification

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Logic Design
RTL Simulation
RTL
Logic Synthesis
Functional Verification
Scan Netlist
Scan Path Design
Functional Verification
Synthesis Netlist
Timing Analysis
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6.1 Logic Simulation
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Logic Design 1HDL Simulation

• Objective
• to correct HDL description by simulating its
  performance and checking its timing due to delays
  of logic circuit.
• Method
• 1. HDL/Logic Simulator

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Logic Design 1Four Valued Logic
Not only 0 and 1, but other values such as
UNKNOWN X, HIGH IMPEDANCE Z are used for the
simulation. Their response are described by truth
table.
Truth Table of AND Gate
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Simulation Method
1. Event Driven Simulation Outputs of the
gates has been evaluated by truth table , only
when an event occurs on inputs of the gates.
Since small portion of whole circuit works
at a time, this scheme avoid waste computation.
Thus, simulator keeps track of those events.

• 2. Time wheel Event Table
• Change of outputs of the gates are stored as an
  event. That event occurs delayed at component
  delay after event of inputs occurs. The time of
  next events are stored in event table. The table
  is considered to be wheel so that it can store
  events of all simulation periods, efficiently.

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Event Driven

• Event is a change of logic value.
• The event entered into a gate may
• generate another event at the output
• of the gate after the gate delay time.
• Event of Signals propagates through
• Logic circuits.
• Event Driven Analysis is to update
• Logic values only when events occur
• at the wire so as to minimize
• computational complexity.
• 30 or less logic parts is running at
• the same time.

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Logic Simulation Example
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6.2 Formal Verification
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Formal Verification
RTL Simulation
RTL
Logic Synthesis
Functional Verification
Scan Netlist
Scan Path Design
Functional Verification
Synthesis Netlist
Timing Analysis
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Logic Design 3Formal Verification

• Objective
• to confirm coincidence between HDL description
  and designed logic circuit. Simulation uses
  various test inputs, while formal verification
  uses equivalence of two functions.
• Method
• BDD method (Binary Decision Diagram)
• It is effective way to show equivalent
  representation of logic functions for two
  targets.
• Problem
• 1. Reduction of scan path flip flops
• 2. Speed up of testing such as concurrent
  testing

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Logic Design 3BDD Representation 1
BDD representation will be unique according to
the best variable order. There was heuristic
algorithm to derive the reduced BDD from original.
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BDD Operation (1)
Merge of 2 isomorphic subgraphs
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BDD Operation (1)
Merge of 2 isomorphic subgraphs
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BDD Operation (2)
Eliminate node, whose son nodes are isomorphic.
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BDD Operation (2)
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Order of nodes
X1 X2 X3 X4 X5 X6
Worst
Best
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Optimal Order Search
0
1
0
1
(B)
(C)
(C)
(B)
(A)
(D)
(A)
(D)
1
0
0
1
f1
f2
f3
f1
f2
f3
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Verification example
X0?X1
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6.3 Timing Analysis
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Timing Analysis

• Timing Analysis is to check the timing violation
  of logic circuits, due to gate delays and wire
  delays. In order to reduce computation, critical
  paths analysis is done by using graph
  representation.
• Pre Layout timing analysis
• Only gate delay is considered.
• Post Layout timing analysis
• Gate delay and wire delay are considered. The
  latter delays are decided by layout pattern. This
  analysis is only performed after layout design.

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Timing Analysis

• Calculate timing of synthesized netlist
• ? Make sure circuit operates correctly under
  specified timing constraints
• Static Timing Analysis (STA)
• ? Timing analysis without input patterns
• -Fast but not accurate
• ? Used after logic synthesis
• Dynamic Timing Analysis
• ? Timing analysis with input patterns
• ? Slow but accurate
• ? Used after physical design with few patterns

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Logic Design 5Timing Analysis (Pre)

• Timing Analysis identifies critical path with
  graph model, instead of exhausted search with
  logic simulator.