A Comparison of Floating Point and Logarithmic Number Systems on FPGAs

1
A Comparison of Floating Point and Logarithmic
Number Systems on FPGAs
Michael Haselman Michael Beauchamp, Aaron Wood,
Scott Hauck University of Washington K. Scott
Hemmert, Keith Underwood Sandia National
Laboratories
Sandia is a multiprogram laboratory operated by
Sandia Corporation, a Lockheed Martin Company,
for the United States Department of Energys
National Nuclear Security Administration under
contract DE-AC04-94AL85000.
2
Introduction

• Floating point
• standard for microprocessors
• many FPGA implementations
• Logarithmic Number System (LNS)
• few FPGA implementations
• similar range
• similar error
• less complexity for some computations
• Create guide for designers

3
Number Systems

• Floating Point
• exceptions (NAN, 0, 8) encoded in exponent and
  significand
• i.e. zero -gt exp.0, sig.0
• implicit 1 before significand
• 1.significand -gt mantissa

4
Implicit Leading 1

• Different ways to express same number
• Standard requires a 1 before radix point

5
Implicit Leading 1

• Different ways to express same number
• Standard requires a 1 before radix point

normalization
6
Number Systems

• LNS
• flags encode exceptions
• 2s comp fixed point number
• dynamic range?

7
IEEE Standard

• single precision

• double precision

FP
LNS
8
FP Multiplication
9
FP Multiplication
10
FP Multiplication
11
Renormalization and Rounding

• (1,2 x (1,2 (1,4
• implicit leading 1 requires possible renorm
• n bit x n bits 2n bits
• round

12
FP Multiplication
1,2)
1,2)
1,4)
1
gtgt1
round
13
LNS Multiplication
comb. logic
14
LNS Multiplication
15
LNS Multiplication
no renormalization! no rounding!
16
FP Division
17
FP Division
18
FP Division
19
FP Division
1,2)
1,2)
.5,2)
1
?
ltlt1
round
20
LNS Division
comb. logic
21
LNS Division
22
LNS Division
no renormalization! no rounding!
23
FP Addition
(greater number)
24
FP Addition
(greater number)
25
FP Addition
(greater number)
gtgt
26
FP Addition
(greater number)
gtgt
27
LNS Addition
comb. logic
28
LNS Addition
(greater number)
??
29
LNS Addition

• Calculating non-linear function
• Look up table
• single precision 8GB
• Interpolation
• Lewis, D.M., An Accurate LNS Arithmetic Unit
  Using Interleaved Memory Function Interpolator

30
Lewis Interpolation

• Stored function values in ROM
• 3 closest points
• 2nd order polynomial

31
Lewis Interpolation

• Stored function values in ROM
• 3 closest points
• 2nd order polynomial
• 3KB single, 6KB double

32
Conversions FP-LNS
comb. logic
33
Conversions FP-LNS

• Evaluating log2(mantissa)
• lookup table
• 24MB for single precision
• linear interpolation
• increased error
• approximations

1.
log2
34
Conversions FP-LNS

• log2(significand) approximations through division
  (Chin-Long Wey)
• One division
• 8KB for single
• 300MB for double
• Many divisions

35
Conversions FP-LNS

• Evaluating 2fraction
• lookup table
• 24MB for single precision
• linear interpolation
• increased error
• Partition and multiply

comb. logic
2fr
36
Conversions FP-LNS

• Evaluating 2fraction
• partition and multiply
• example

37
Conversions FP-LNS

• Evaluating 2fraction
• partition and multiply
• example

38
Conversions FP-LNS

• Evaluating 2fraction
• partition and multiply
• example
• reduce memory by cube root
• introduces multiplies

39
Implementation

• Parameterized LNS and conversion library written
  in Verilog
• Floating point library from Sandia
• Mapped to VirtexII 2000

40
Area Metric

• BRAM 28 slices
• Mults 18 slices

mult
BRAM
slices
41
Multiplier Sizes
27x
18x
42
Divider Size
94x
46x
43
Adder Sizes
4x
3x
44
Converter Sizes
45
Applications
multiplies and divides


/
LNS
/


46
Applications
addition



FP



47
Applications
mixed


/
??



48
Area Break Even Point mult/div vs. add
LNS
LNS
LNS
LNS
FP
FP
FP
FP
single
double
49
Applications
LNS operations FP I/O
FP

FP

Convert
/
??

Convert


LNS
50
Conversion Area Overhead
LNS
FP
51
Conversion Area Overhead
LNS
FP
52
Conversion Area Overhead
LNS
FP
53
Performance Metric

• Latency of Circuit
• Time from input to output
• Acyclic circuits
• Circuit dependent

54
Latency Data
mult
div
add
55
Applications
mixed circuit critical path



/
??
/


56
Performance Break Even Point mult/div vs. add
LNS
LNS
LNS
LNS
FP
FP
FP
FP
single
double
57
Conclusion

• Area
• No conversion
• gt70 mults vs. adds to make LNS smaller
• gt45 div vs. adds to make LNS smaller
• With Conversion (FP-LNS-FP)
• Benefits must outweigh converter overhead
• Ex
• At most 1 convert per 4 ops in mult-single
• At most 1 convert per 10 ops in mult-double

58
Conclusion

• Performance
• Single precision
• gt46 mults vs. adds to make LNS faster
• gt25 div vs. adds to make LNS faster
• Double precision
• gt36 mults vs. adds to make LNS faster
• gt10 div vs. adds to make LNS faster

59
A Comparison of Floating Point and Logarithmic
Number Systems on FPGAs
Michael Haselman Michael Beauchamp, Aaron Wood,
Scott Hauck University of Washington K. Scott
Hemmert, Keith Underwood Sandia National
Laboratories
Sandia is a multiprogram laboratory operated by
Sandia Corporation, a Lockheed Martin Company,
for the United States Department of Energys
National Nuclear Security Administration under
contract DE-AC04-94AL85000.