The CMS Pixel Detector

1
The CMS Pixel Detector
Steve Schnetzer Rutgers University

• Overview
• Structure
• Electronics
• Sensors
• Bump Bonding
• Performance

2
CMS Pixel Institutions
Barrel Aachen, Basel, ETHZ, PSI, Zurich
Disks Davis, FNAL, Johns Hopkins,
Mississippi, Northwestern,
Purdue, Rutgers
General HEPHY Vienna
Close collaboration between barrel and disks
Common Electronics Sensors
Readout system
3
Design Overview

• Geometry
• 3 Barrel Layers
• 2 Pairs of Forward/Backward Disks
• ? 3 high
  resolution space points for ? ? 2.2
• Resolution
• Charge sharing from Lorentz drift (4T field)
• 150 ?m x 150 ?m
  pixels
• ? 15 ?m in
  both r? and z
• Readout
• Full analog readout
• - pixel pulse
  height
• - analog coded
  row/column addresses
• Radiation tolerance

4
Lorentz Angle

• Large Lorentz angle 28o in 4 T field
• ? r? resolution from charge sharing
• ? square pixels
• ? analog readout
• ? n pixels on n-silicon
• type inversion after irradiation
• operate partially deplete
• ? square 150 ?m x 150 ?m pixels

? ? (r?) ? 10 ?m ? (z) ? 17 ?m
5
Geometry

Barrel
Three Layers r 4.3 cm, 7.2 cm, 11.0 cm
z ? 26 cm
Inner two layers (initial low luminosity) Outer
two layers (high luminosity)
Disks
Two Disks z 33.7 cm, 46.5 cm
inner radius 6.0 cm
outer radius 15.0 cm
6
Barrel Modules
Layers consist of Ladders
? 8 Modules / Ladder
Total 800 Modules in 3 layers
Module

• 2 x 8 array of 16 Readout Chips (ROCs)
• Sensor on top of ROCs
• Kapton hybrid on top of Sensor
• 2 data links / Module (inner layer)
• 1 data link / Module (outer 2 layers)

7
Disk Blades

• Disk consists of 24 Blades
• Blades rotated by 20o for charge sharing
• Lorentz drift
• track inclination

• 4 (3) plaquettes on front (back) sides
• Total of 45 ROCs
• Sensor on top of ROCs
• ROCs on top of hybrid
• 2 data links / Side

8
Readout Chip (ROC)
Column drain architecture

• Fast Column OR ? token scan of double column
• scanning speed 2 GHz
• double hit capability
• Address/pulse height of hit pixels ? periphery
• Time stamp and data buffers _at_ periphery
• Trigger verification

9
Readout Chip (ROC)
Column periphery

• 8 deep time stamp buffer / double column ? lt
  0.1 dead time
• 24 deep data buffer / double column
  ? lt 0.1 dead time
• Octal coded pixel address
• Pulse height
• Trigger verification
• Write and search counters
• Search delayed by trigger latency

10
Readout Chip (ROC)
Pixel Unit Cell

• Preamplifier and shaper
• DC - coupled sensor ? absorb leakage current
• Global pixel threshold local 3-bit trim
• Column row addressing
• Comparator disabled after hit

• programming
• calibration

11
Status of ROC

• PSI41 (DMILL) received 4/01
• Detailed testing still ongoing
• Basic functionality OK!
• Pixel Unit Cell works
• CDA mechanism OK (2.05 GHZ)
• Time stamp and data buffers OK
• Event assembly readout works correctly
• Readout amplifier chain too slow !!
• ? data buffer read amplifier
  (fixed)
• Clocking transients on analog output signal !!
• ? poor amplifier power rail design
  (fixed)
• Limits practical readout speed to 15 MHz
• DMILL chip yield poor

• 36 x 40
• final column drain architecture
• no control interface block

• 52 x 53 (full size)
• final architecture
• fixes implemented
• control interface block
• DACs, regulators, I2C, drivers

12
Token Bit Manager (TBM)

• one TBM per data link
• located on barrel modules / disk blades
• controls readout of group of ROCs through token
  pass
• writes token pass header and trailer
• passes triggers, clocks, resets to ROCs
• stacks triggers awaiting token pass
• prototype in DMILL (submission) next week
• translation to 0.25 micron for final chip

13
Control Network

• Programming of front-end chips
• ROC
• pixel thresholds
• trigger latency
• set calibration mode
• TBM
• enable/disable passing of triggers/tokens
• reset
• Laser Driver
• threshold bias current
• SEUs ?
• ROC thresholds reset frequently

14
Control Network Architecture

• Control Network Hub (CNH)
• incorporated in dual TBM chip
• sits on blade /modules
• sends control commands to front-end chips
• TBM, ROC, PLL
• Front-End Controller (FEC)
• VME module
• sits in control room
• sends to front-end
• 40 MHz Clock and Trigger
• Front-end control signals
• one channel per link
• serves as sole master of link

15
Control Network HUB (CNH)

• 32 CNHs addressable on each link
• Adjustable clocking speed
• 100 kHz TBM, PLL, Laser driver
• 40 MHz ROC
• Ports per CNH
• 4 fast external
• 1 slow external
• 1 slow internal

Front-End Controller (FEC)

• VME module
• Based on Xylinx FPGA
• 8 - 16 Mbyte of external memory
• storage of pixel thresholds
• 8 channels (links) per module
• For each channel
• 40 MHz CMS clock with embedded trigger (out)
• control clock (100kHz - 40 MHz) (out)
• control data (out)
• control data (in)
• Coupled to CMS TTC system

16
Sensor Design

• Lorentz drift of electrons ? pixels n
• Partially depletion ? n on n
• after type inversion depletion
  from pixel side
• Radiation ? operate partially depleted
• bias up to 300 V
• Stable up to 500 V ? guard rings on p-side
• sensor
  edges at ground potential
• p-stop isolation of pixels
• inter-pixel resistance 106 to 109
  ohms
• ? IV-test certification of
  wafers
• ? limit potential of
  unconnected pixels

17
Sensor Results

• 11 guard ring design best
• holds 1000 V

• Double p-stop rings
• after 1 x 1014 neq/cm2
• exponential current increase above 300 V
• due to 3 of pixels
• not correlated with unbonded
  pixels

18
Pixel Isolation
double p-ring single p-ring
single p-ring plus cross
Singe p-stop design provides best wafer
certification capability
19
Diamond
Possible rad-hard alternative sensor

• Beam Test
• PSI30 Honeywell chip
• 12 GeV incident protons

• low leakage current
• no cooling required

Mean Pulse Height 7700 electrons (summed
over 9 pixels)
Average Efficiency 94

• Coming
• improved diamond
• side-by-side comparison
• Si diamond
• before/after irradiation

20
Bump Bonding
PSI Process
Indium Connectivity yield 3955/3960
0.9987
MCNC Process
Pb/Sn Connectivity yield 0.9999
Placement yield 134/135 0.993
? 10 loss for 16-chip placement
Working on thinning and processing 8-in
wafer
AMS Process
Indium Yield comparable to MCNC
(ATLAS) Already bumped and bonded 8-in
wafers (ALICE)
21
Data Readout Rates Times
LHC high luminosity
Tracks/event 800 (? ? 2.2)
100 (pT ? 1 GeV) Pixel hits/event 13k
for 7cm layer
occupancy ? 3.3 x 10-4
pixel hits/module ? 15
pixel hits/ROC ? 1 single
pixel rate ? 10kHz Data volume 40kB/event
4 GB/s at 100 kHz Readout
Times Readout speed 40
MHz Number of optical links
? 1500 Trigger rate 100kHz
7 cm layer
ROCs/link 16
Pixel hits/link
15 ? 9 Readout
time (?s) 5
Max time (?s) 13
Wait time (?s) 2.4
22
Pixel Hit Resolution

• 7 cm barrel layer
• 100 GeV ? tracks

Depletion thickness (?m) pixel pitch (?m)
200 ?m depletion, 150 ?m pitch

• ?(r?) ? 10 ?m (all ? up to 2.2)
• ?(z) ? 20 ?m (0.4 lt ? lt 2.2)

23
Primary Vertex Identification
_
SUSY Higgs events h b b
? ? ?

• 3 barrel / 2 disk pairs
• high luminosity
• Only pixel hits used

Resolution
?PV ? 50 ?m all channels
24
Summary

• Configuration
• 3 barrel layers 2 pairs of disks
• ? 3 space points for ? lt 2.2
• Resolution
• charge sharing from Lorentz angle
• ?(r?) lt 15 ?m
• Readout Chip
• pixel unit cell works
• column drain architecture works
• column periphery problems identified/fixed
• DMILL final chip submitted next month
• translation to 0.25 ?m half year
• Control Network
• designed to work at speeds up to 40 MHz
• ? fast refresh of pixel
  thresholds
• FEC ? hub connection tested in spring