ECE 583 Design with Programmable Logic

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ECE 583Design with Programmable Logic

• Dr. Kuan Zhou
• Kingsbury W223
• kuan.zhou_at_unh.edu

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Lecture 1

• Introduction

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Organization

• Syllabus
• Motivation
• Levels of abstraction
• Digital system design
• VHDL and Basic modeling concepts
• Summary

(some slides are modified from Prof. Chathas
CSE517 slides)
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Syllabus

• Course goals
• Develop an understanding of advanced hardware
  design practices,
• Understand levels of design abstraction,
• Ability to effectively apply HDL and CAD tools
  for specification, simulation and synthesis,
• Ability to handle large designs and related
  integration problems,
• Knowledge of testing and design for testability.

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Syllabus

• Textbook
• Optional VHDL Design Representation and
  Synthesis by J.R. Armstrong and E.G. Gray.
• Required Peter Ashendens The designers guide
  to VHDL, 2nd edition, Morgan Kaufmann publishers
• Evaluation
• Homework (25 )
• Lab Projects (40 ).
• Two Midterms (20 ).
• Final exam (15 ).

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Syllabus

• Grading policy
• gt2/3 A.
• gt1/3, lt 2/3 B.
• gt0, lt 1/3 C.
• lt F.
• Assignments turn in policy
• All assignments are to be submitted in the
  classroom on the due date.
• Assignments turned in later will lose 10 of
  their grade for each delayed day.
• Tools for programming assignments and project
• VHDL simulator
• Xilinx ISE Foundation series

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Syllabus

• Course website
• http//www.ece.unh.edu/courses/ece523/
• Office hours
• 3 pm to 4 pm on Wednesdays and Fridays.
• Exceptions will be announced.
• Welcome to walk in to the office if the door is
  open.
• Alternative schedule an appointment.
• TA no TA

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Syllabus

• Midterm exam I date February 25th, 2006
• Midterm exam II date April 7th, 2006
• Final exam date TBA

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Project Reports

• Requirements specification
• Word processed, submit postscript or pdf
• Schematics, computer drawn.
• No optically scanned, handwritten information
• allowed
• Professional
• Organization
• Grammar and spelling
• Where you demonstrate your grasp of the material

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Required Student ComputingCapabilities

• Internet access for lecture streaming, ftp file
• transfer, telnet remote execution (Windows or
• UNIX)
• ASCII file editing, word processing, waveform
• and schematic viewing (Windows or UNIX)
• Local software execution on PC (license check
• out via Internet)

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Goal Details

• To learn the detailed syntax and semantics of a
  hardware description language (VHDL).
• To learn the tool set that supports the
  language.
• To apply the language to modeling and synthesis
  of digital systems at varying levels of
  abstraction.
• Language Comparison (VHDL vs. Verilog).
• System level modeling with SystemC.

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General Prerequisites

• Knowledge of gate level design
• Knowledge of computer organization
• Knowledge of a high level programming language
  (C or C preferred)
• ECE Prerequisite Courses
• ECE 562 Computer Organization
• ECE 543 Introduction to Digital Systems
• CS 415 Intro. to Comp. Programming w/ Java
• Ability to troubleshoot and make a program work

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Definition of an HDL

• Def A high level programming language used to
  model hardware.
• special hardware related constructs
• digital (now) and analog (VHDL-AMS)
• models used for documentation, simulation,
  synthesis, and test generation
• have been extended to the system design level

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Language Semantics

• Semantics what is the meaning of a language
  construct?
• HDLs have different semantics for different
  applications
• Simulation
• Synthesis
• Test
• In this course we will be concerned with
  simulation and synthesis semantics.

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Announcement

• Sun and Linux Accounts Username Last Middle
  First Password pw

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entity T_FF is
port(RESET,T,CLK in STD_LOGIC QOUT out
STD_LOGIC)
end T_FF
architecture ALG of T_FF is
signal Q STD_LOGIC
begin
process(RESET,T,CLK)
begin
if (RESET '1') then
Q lt '0'
elsif (CLK'EVENT and CLK '1') then
if T '1' then
Q lt not Q
end if
T Flip-flop Description
end if
end process
QOUT lt Q
end ALG
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Simulation Semantics what happens when you
simulate it?
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Synthesis Semantics what kind of circuit is
synthesized?
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VHDL

• VHSIC Hardware Description Language
• Very High Speed Integrated Circuit Program
• DOD began development in 1983
• design exchange among VHSIC contractors
• document parts with long functional life
• IEEE Standardization
• Standardization process began in 1985
• IEEE Standard 1076 in 1987
• Updated in 1993

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Administrative stuffs

• Bookstore has contacted the sales
  representative.
• The DAL entrance code is 57321. Its in Room
  S324, Kingsbury.
• A test email will be sent to all the students
  this weekend

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Significance of VHDL

• VHDL provides a text based approach to
  structured hardware modeling and design.
• Analogous to high level software languages such
  as PASCAL, C, C, and JAVA.
• An important tool in managing the complexity of
  VLSI systems.

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Verilog

• A C like HDL which is very effective in ASIC
  design
• Simpler than VHDL
• Good for RTL and gate level design, cumbersome
  for behavioral modeling
• Developed and largely controlled by Cadence,
  although officially a standard

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System C

• A system level modeling language
• Create a model then
• partition the model into hardware and software
  portions
• each portion can synthesized (hdw) or compiled
  into code (soft)
• Special classes of C
• Industry standard (systemc.org)

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System On A Chip
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Language Comparison

• Which language is best for
• A particular level of abstraction?
• A particular application?
• Which language is the most simulation and/or
• synthesis efficient?
• Which language is
• Easiest to learn?
• Easiest to model with?

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Summary

• Hardware description and system level modeling
  languages are a critical part of the system
  design process
• Learning them will teach you a lot about
• Languages and data structures
• Computer hardware structures
• System design process