ESD Design and Layout Requirements Huang BinFeng MiDAS Lab

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ESD Design and Layout Requirements

• Huang BinFeng
• MiDAS Lab. C.N.U
• 2003. 11. 10

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Contents

• Introduction
• What is ESD
• Design and layout requirement
• Design concepts
• Thick Filed Device
• nMOS Transistors (FPDs)
• Gate-Coupled nMOS (GCNMOS)
• SCR Protection Device
• ESD Protection Design Synthesis
• Total Input Protection

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What is ESD?

• ESD Electrostatic Discharge
• Generation
• -- Triboelectric (friction causes
  accumulation of charge)
• -- Induction (field induces charge)
• Discharge
• -- Dielectric (air) breakdown
• Electric field increases when charged
  bodies approach
• each other
• -- Current flow into circuitry
• ESD stress modes
• -- Human Body Model (HBM)
• -- Machine model (MM)
• -- Charged Device Model (CMD)

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Design Concepts
Serves to limit the voltage or current at the
circuit being protect until the primary device is
fully operational.
Will shunt most or all of the current during an
ESD event

• Can be
• a thick field transistor
• a silicon controlled rectifier(SCR)
• a nMOS transistor
• a simple pn diode

• Can be
• a small grounded gate MOS transistor
• a diode between the pads and the power/ground
  supplies

• Can be
• polysilicon
• n diffusion
• p diffusion
• n-well

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Thick Field Device
--thick oxide or field oxide device (FOD) --used
for technologies with feature sizes (ranging from
3µm to 1µm)
Three Different cross-sections
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Main Design Parameters of the FOD
HBM failure thresholds increase as the channel
length is decreased in the 7µm to 2µm range
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Drain contact

• Impact of the contact spacing
• very important for the abrupt junction processes,
• weak effect for lightly doped drain (LDD)
• the effect virtually vanishes for silicide process

Increased-saturate reason distance between the
heat source and the contact (contact close to
diffusion edgethe produced heat spread to heat
the contact metalizationresult in a lower
failure voltage)
Improve the hot carrier reliability
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nMOS Transistors (FPDs)

• essentially thin oxide devices as opposed to the
  FOD
• are also called field-plated diodes or
  gated-diodes
• used as a primary protection device, in
  technologies with feature sizes greated than 1µm

• turn around in the ESD performance of the nMOS
  device
• at the 0.8µm technology node for non-silicided
  devices
• at the 1µm technology node for silicided device

nonsilicided technology
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Main design parameters of nMOS and layout

• RF is composed of
• metal finger resistance
• Contact resistance
• Diffusion sheet resistance
• Rs (parasitic resistance)
• Associate with the ground bus that
  connects the fingers of the device

• the transistor channel length (L)
• drain contact-to-gate spacing (DCG)
• the device width (not shown)
• The source contact-to-gate spacing (SCG) (not
  play much of a role, often kept at its minimum
  design value.

minimizing Rs will give more uniform current
distribution
Maintaining a minimum rate for Rs/RF is important
for obtaining the best possible ESD performance.
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HBM ESD performance in FPDs as a function of DCG

• drain contact spacing has a large effect for
  nonsilicided processes.
• optimum spacing is approximately 6µm
• for the silicided cases, no obvious dependence on
  drain contact spacing

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Gate-Coupled nMOS (GCNMOS)
If gate voltage is about 1V, nMOS trigger is
lowered to less than the onset for avalanche
breakdown Vt1ltVt1,(ideal for improved ESD
protection. If gate voltage goes above 5V, It2
decreases to give reduced failure threshold
voltage It2ltIt2 A gate voltage of between 1 and
2V is typically needed for best ESD performance
In most applicationsthin gate devices is used
with its gate grounded. Howevercan be a more
robust protectiongate is coupled high
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GCNMOS

• using SPICE
• time constant for the gate discharge will depend
  on the ESD current level and the size of the
  field oxide device width.
• usually design gate stays on for a minimum
  duration of between 5 and 10 ns corresponding to
  the rise time of the ESD event allow enough
  time for all the fingers to turn on.

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ESD Failure Distribution

• Width dependence
• Excellent ESD level

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GCNMOS

• the reduction in Vt1 beyond the transistor
  threshold of approximately 1V is apparent and in
  agreement Fig.6.17
• slight increase in Vt1 at higher gate bias
  (attributed to the reduction in the substrate
  current occurs around 3V.

In epi or bulk substrate gate bias in excess will
degrade It2, possible because of channel heating
effect
for efficient multifinger turn on of the nMOS
protection device, the Vt1 value needs to be less
than the Vt2 value
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GCNMOS I/O Applications
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SCR Protection Device
Silicon Controlled Rectifier (SCR)

• Process controlled parameters
• Holding voltage controlled by the n-well overlap
  of the p anode (X)
• The trigger voltage determined by the p-substrate
  resistance Rp.
• thicker epitaxial layer is desirable for better
  ESD performance
• a thinner expitaxial layer is required for
  reducing the CMOS latchup sensitivity in advanced
  VLSI chips

During an ESD stress pulsecollect-base junction
of npn goes into avalanche breakdowngenerating
the electron current in the n-wellforward biases
the emitter-base junction of the pnpSCR is
turned ondevice in lower impedenceanode to
cathode clamping voltage is 1-2Vreduces the
power dissipationimprove ESD performance

• process parameters that influence the trigger
  voltage n-well, substrate doping levels
• main design parameter influencing the trigger
  voltage X,Y

• The performance of the device
• (60-70V µm-1) in non-silicided processes
• (40-50V µm-1) in silicided processes
• performance so high, difference is not that
  important

X,Y trigger level lower leakage increase
below 3 µm the SCR trigger voltage drops sharply
whereas the leakage current increases
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MLSCR (modified LSCR)
to reduce the trigger voltage without
significantly impacting the leakage current, the
design is modified to include a highly doped
region near the surface at the n-well edge.
low-voltage trigger SCR (LVTSCT) by replacing the
field oxide of the MLSCR with the thin
oxide essentially uses an MOS device in parallel
with the SCR. low trigger voltage can be
used as an ESD protection device for CMOS output
buffers.
trigger voltage be reduced to 12-15V
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Design and layout of the SCR devices
spacing A determine the leakage
spacing B is not very critical and can be
collapsed as long as the process is
nonsilicide. for a silicide process, kept at a
minimum to improve the gain of the lateral
devices.
spacing C and C are process defined parameters,
should be kept at a minimum.
spacing D (channel length of the MOS device) will
control the trigger, is kept at a minimum.
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layout
for silicided process series resistor needs to
be much longer because of the low sheet
resitivity of the silicided diffusion
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ESD protection design synthesis
this behavior in MLSCR could be caused by the
additional impedance in the device conduction
path introduced by n at the well boundary.
SCR Primary Protection
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Secondary Protection Devices
the secondary protection device needs to be able
to carry some current before the primary
protection device is triggered. This requirement
is applicable only for the SCR protection design
schemes where the trigger voltage is relatively
higher than the input gate oxide break down under
ESD conditions.
a grounded nMOS with a series resistor is needed
the device goes into npn snapback after the drain
avalanche breakdown at about 14V. at higher
current pulses the device eventually enters the
thermal second breakdown region, which eventually
leads to failure. the ESD failure threshold level
has been correlated to the second breakdown
trigger current level.
Field Plate Diode
Isolation Resistor

• diffusion resistor
• n-well resistor
• polysilicon resistor

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protection scheme

• 23 general increase in the protection level
  with inclusion of the FPD device
• 1 FPD by itself can offer some protection,
  which is enhanced by adding the resistor/diode
  combination.
• 4 the diode/resistor has a limited effect
  on improving the failure level as increasing the
  resistor size does not further enhance it.
• 5,6,7 the minimum failure level increase
  for the smaller resistor

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Con.
at the higher current levels the resistor seems
to heat up causing an increase in the resistance,
where the onset of heating is indicated by
arrows. the heating effect seems to be minimum
for the widest resistor. the heating effect is
not observed for the diffusion resistors.
pad voltage build up is continuous without any
breakdown
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total input protection
when the current level reaches 100mA the voltage
at the high end of the resistor approaches 25V,
which is equal to a 15V drop across the resistor
plus the FPD snapback voltage of 8V, this
triggers the MLSCR device and the current level
abruptly increases by 200mA
inputs with diffusion resistor

• 1 FPD by itself cannot trigger the SCR
  device since its breakdown voltage is lower
• 2 diffusion resistor alone in parallel
  with the SCR cannot obvious have an impact on the
  SCR function
• 3 both the FPD and the resistor are
  combined, full effective SCR protection for
  inputs is achieved.

the value of the resistor Vsp snapback
holding voltage of the RPD Vtrig trigger
voltage of the primary device It2 the second
breakdown trigger current
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inputs with polysilicon resistor
SCR trigger occurs below the failure current, the
protection scheme would effective, the MLSCR is
observed to trigger at a low current level of
150mA, following the MLSCR trigger, the current
level increases by about 330mA, which is more
than for the diffusion resistor case. (indicate
after MLSCR triggers, most of the current flows
through this device, removing all of the stress
from the polysilicon resistor.
the protection for the polysilicon resistor all
worked well
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polysilicon resistor reliability

• both 200V and 400V stress levels there is no
  physical damage to the polysilicon resistor.
• at 600V level, the first indication of heating is
  seen at the tapered portion of the resistor.
  (improve the layout to reduce this effect).
• at 800 and 900V levels there is obviously severe
  damage to the resistor that was not electrically
  detectable since a continuous polysilicon
  filament is present. for the 900 stress level
  some contact damage is also present, indicating
  that the current density through each contact
  exceeds the failure level. (can be improved by
  increasing the number of contacts).
• at 1000V stress the polysilicon is completely
  blown giving rise to an open failure.

FPD
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Thank you !