VLSI Digital System Design

1
VLSI Digital System Design

• Input-Output Pads

2
Input-Output Pad Design

• I-O pad design is highly specialized
• Requires circuit design experience
• Requires fabrication process understanding
• Choose already-characterized library from
• Fabrication vendor
• Third-party library vendor
• In-house group

3
Pad Size and Spacing

• Pad size
• Smallest to which a wire can be bonded
• 100 150 µm
• Pad spacing
• Smallest to which a bonding machine can bond
• 150 200 µm

4
Interdigitated Pads

• Allows more pads on die

5
IBM C4 I-O Pads

• Bonding wires restrict I-O pads to die edge
• IBM C4 I-O pads can also be on interior of chip
• Deposit solder ball on I-O pad
• Heat die and board to reflow solder
• Solder surface tension positions die on board

6
Latchup

• Latchup occurs when voltage excursion outside VSS
  lt v lt VDD
• Most likely at I-O pad
• Large transistors
• High current
• Inductance of bonding wire
• Connection to external circuitry

7
Output Pad Latchup Prevention

• Separate the nMOS and pMOS transistors
• Separate the power supplies for I-O frominternal
  logic
• Guard rings

8
Guard Rings

• Ohmic contacts to metal
• p diffusion in p-substrate
• n diffusion in n-well
• Collect minority carriers
• Injected into substrate whendrain diodes are
  forward-biased
• Rings should be continuous diffusion
• No crossovers

9
Double Guard Rings

• Surround nMOS transistor by
• p connection to VSS, surrounded by
• n-well with n connection to VDD
• Surround pMOS transistor by
• p ring connected to VDD, surrounded by
• n-well with n connection to VSS

10
Use Smaller Transistors in Parallel

• Minimize gate
• Reduce RC delay
• I-O pad transistors often have long gates
• Improve avalanche breakdown characteristics
• Parallel metal-transistor connections
• Minimize metal migration

11
Input PadElectrostatic Discharge Protection

R
X
Inputpad
12
Input Pad ESD Protection

• If not VDD lt X lt VSS,one of the clamp diodes
  turns on
• Use double guard rings
• Resistor R limits current in clamp diode
• 200 O lt R lt 3000 O
• Tub resistor
• For n-well process p-diffusion
• C is input capacitance
• Speed of signal limited by RC

13
Alternative Input Pad ESD Protection
R
X
Inputpad
14
Punch-Through Device

• Built of closely-spacedsource and drain
  diffusions
• No gate
• Avalanches at c. 50 V

15
Pull-Up or Pull-Down Resistor

• Long pMOS transistor
• Long nMOS transistor
• Connect gate to signal for IDDQ testing